[llvm] [AMDGPU][MC] GFX9 - allow op_sel in v_interp_p2_f16 (PR #150712)

[Jun Wang via llvm-commits]

jwanggit86 wrote:

> Can you please add a few assembly tests with 3 values in op_sel? like `'... op_sel:[1,0,1]'`

Good suggestion! This, however, revealed a problem in the code. Because we are now using `printPackedModifier()` to print the instruction. Even with the code change there, it only prints 3 bits (because there's no src0). This is at odds with the ISA doc, which states op_sel[3] is for dst (actually the other bits are not used).

Additionally, when we parse the instruction, the bits are interpreted differently from the printer. For example, for `v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,0,1]`, the 3 bits are 0 (for src0), 0 (for src 1 and ignored), 1 (for src2). So the printer prints `v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[0,1,0]`. Obviously there's the round-trip issue here. This problem can be fixed, but the problem with using `printPackedModifier()` is more difficult. I'm thinking that `printPackedModifier()` should not be used. Come to think of it, I think the 1st commit was actually correct, except it does not print the original bits for src0-src2 in the input instruction.

Is there any objection to reverting to the 1st commit? @Sisyph I'll see if I can modify it to print the original bits but I don't think we should use `printPackedModifier()`.



https://github.com/llvm/llvm-project/pull/150712