[llvm] [AMDGPU] Use fake16 load/store with +real-true16 and sram-ecc (PR #161256)

[Brox Chen via llvm-commits]

broxigarchen wrote:

I think there are two issues:

1. We can not simply use the16bit load/store fake16 pattern in true16 mode, since these has dst 16bit type but put it in a vgpr32 and isel will generate mismatched-size `vgpr16 = COPY vgpr32`. We need to insert additional EXTRACT_SUBREG for these patterns in true16 mode.

I previously created a draft patch to address another D16 issue and its approach is similiar to this patch -- disabled D16 patterns for true16.  https://github.com/llvm/llvm-project/pull/156574 put it here for reference

2. We might need to turn off D16 for spills. For example, spillv16.ll still has scratch_load_d16_b16. It sounds like we need to spill/restore a hi16/lo16 within a vgpr32 and I am not sure what is the best way to approach this. Maybe we need to construct a vgpr32 from a vgpr16 and spill/restore it?

https://github.com/llvm/llvm-project/pull/161256