[llvm] [X86] Create special case for (a-b) - (a<b) -> sbb a, b (PR #161388)
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Tue Sep 30 07:49:45 PDT 2025
https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/161388
None
>From af8fe5c9fd3a1f2d6be92ddf6d55332ef8a47d65 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 30 Sep 2025 10:20:41 -0400
Subject: [PATCH 1/2] Pre-commit test (NFC)
---
llvm/test/CodeGen/X86/sbb.ll | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/llvm/test/CodeGen/X86/sbb.ll b/llvm/test/CodeGen/X86/sbb.ll
index 78d609d3a17e6..496e5d01fc2db 100644
--- a/llvm/test/CodeGen/X86/sbb.ll
+++ b/llvm/test/CodeGen/X86/sbb.ll
@@ -365,3 +365,19 @@ define i32 @uge_sext_add(i32 %0, i32 %1, i32 %2) {
%6 = add nsw i32 %5, %0
ret i32 %6
}
+
+define i32 @sub_sub_ugt(i32 %a, i32 %b) {
+; CHECK-LABEL: sub_sub_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: subl %esi, %eax
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %cmp = icmp ugt i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ %sub = sub i32 %a, %b
+ %res = sub i32 %sub, %conv
+ ret i32 %res
+}
>From 59dc6570735321025e0da5430a0e51503b7e372f Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 30 Sep 2025 10:47:19 -0400
Subject: [PATCH 2/2] [X86] Create special case for (a-b) - (a< b) -> sbb a, b
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 10 ++++++++++
llvm/test/CodeGen/X86/sbb.ll | 6 ++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cd04ff5bc7ef4..23861913d36a1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -52380,6 +52380,16 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
DAG.getVTList(VT, MVT::i32), X,
DAG.getConstant(0, DL, VT), NewEFLAGS);
}
+
+ if (IsSub && X.getOpcode() == X86ISD::SUB && X.getValueType().isInteger() &&
+ EFLAGS == X.getValue(1) && !isa<ConstantSDNode>(X.getOperand(1))) {
+ SDValue NewSub =
+ DAG.getNode(X86ISD::SUB, SDLoc(X), X.getNode()->getVTList(),
+ X.getOperand(1), X.getOperand(0));
+ SDValue NewEFLAGS = NewSub.getValue(1);
+ return DAG.getNode(X86ISD::SBB, DL, DAG.getVTList(VT, MVT::i32),
+ X.getOperand(0), X.getOperand(1), NewEFLAGS);
+ }
}
if (CC == X86::COND_AE) {
diff --git a/llvm/test/CodeGen/X86/sbb.ll b/llvm/test/CodeGen/X86/sbb.ll
index 496e5d01fc2db..579608b628582 100644
--- a/llvm/test/CodeGen/X86/sbb.ll
+++ b/llvm/test/CodeGen/X86/sbb.ll
@@ -370,10 +370,8 @@ define i32 @sub_sub_ugt(i32 %a, i32 %b) {
; CHECK-LABEL: sub_sub_ugt:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: subl %esi, %eax
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: cmpl %edi, %esi
+; CHECK-NEXT: sbbl %esi, %eax
; CHECK-NEXT: retq
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
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