[llvm] Fold SVE mul and mul_u to neg during isel (PR #160828)

[Martin Wehking via llvm-commits]

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@@ -723,6 +723,19 @@ class SVE2p1_Cvt_VG2_Pat<string name, SDPatternOperator intrinsic, ValueType out
     : Pat<(out_vt (intrinsic in_vt:$Zn1, in_vt:$Zn2)),
                   (!cast<Instruction>(name) (REG_SEQUENCE ZPR2Mul2, in_vt:$Zn1, zsub0, in_vt:$Zn2, zsub1))>;
 
+class SVE_2_Op_Neg_One_Passthru_Pat<ValueType vt, SDPatternOperator op, ValueType pt,
+                             Instruction inst, ValueType immT>
+: Pat<(vt (op pt:$Op1, vt:$Op2, (vt (splat_vector (immT -1))))),
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MartinWehking wrote:

Hi, thanks, that's something which has made me think about it a lot.

I don't think it's needed here. AArch64bic is a PatFrags that is used generically for all patterns that might occur. As far as I know, only for a splat vector of type "nxv2i64", the 64 bit splat is required.

I created multiple patterns where the splat value dataype is provided as a parameter.
Similar to other patterns (e.g. the ones listed under "// SVE2 integer add/subtract wide "  (and the SelectionDAG I saw) the type is either 32bit for the immediate when the result vector is not  "nxv2i64" or 64bit when it is.
I'm assuming due to type legalization there won't be any e.g. i16 bit type.

If there is the possibility for initializing a splat_vector is wrong and there is a valid 64 bit splat for e.g. a non `nxv2i64` then this needs to be adapted. Please also correct me if there is a misunderstanding from my side.


https://github.com/llvm/llvm-project/pull/160828