[llvm] [RISCV] Add commutative support for Qualcomm uC Xqcics extension (PR #161328)
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Tue Sep 30 00:20:54 PDT 2025
https://github.com/hchandel created https://github.com/llvm/llvm-project/pull/161328
This is a follow-up to #160653 doing similar changes for Xqcics.
>From ed905d66917fc600942f6767a9c51dd9356e9abb Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Mon, 29 Sep 2025 12:13:02 +0530
Subject: [PATCH 1/4] [RISCV] Add commutative support for Xqcics
Change-Id: Id19e34ae05007849f416429b7eb1d4b1d7c4d682
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 13 +++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 4 ++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 56db09a286547..4812fb981085d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3762,6 +3762,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
return false;
// Operands 1 and 2 are commutable, if we switch the opcode.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
+ case RISCV::QC_SELECTIEQ:
+ case RISCV::QC_SELECTINE:
+ case RISCV::QC_SELECTIIEQ:
+ case RISCV::QC_SELECTIINE:
+ return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
case RISCV::TH_MULA:
case RISCV::TH_MULAW:
case RISCV::TH_MULAH:
@@ -3974,6 +3979,14 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
+ case RISCV::QC_SELECTIEQ:
+ case RISCV::QC_SELECTINE:
+ case RISCV::QC_SELECTIIEQ:
+ case RISCV::QC_SELECTIINE: {
+ auto &WorkingMI = cloneIfNew(MI);
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
case RISCV::PseudoCCMOVGPRNoX0:
case RISCV::PseudoCCMOVGPR: {
// CCMOV can be commuted by inverting the condition.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 13b02d1b2d6db..b6e790c4ecd7b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -524,7 +524,7 @@ class QCIRVInstRI<bits<1> funct1, DAGOperand InTyImm11,
let Inst{30-20} = imm11;
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCISELECTIICC<bits<3> funct3, string opcodestr>
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2),
@@ -537,7 +537,7 @@ class QCISELECTIICC<bits<3> funct3, string opcodestr>
let rs2 = simm1;
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCISELECTICC<bits<3> funct3, string opcodestr>
: RVInstR4<0b01, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2),
>From 5f3308f80cc3b97fad8cf6a70d98f0e95e30bdfc Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Mon, 29 Sep 2025 12:14:13 +0530
Subject: [PATCH 2/4] Precommit xqcics.ll with avoidable moves
Change-Id: I9cb0ef038b3d1de5234d2c464b0b100f9e39f361
---
llvm/test/CodeGen/RISCV/xqcics.ll | 134 ++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 38de8fbd78b36..80f9c19e7caaf 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -690,3 +690,137 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq1:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a1, a0, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq1:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieq a1, a0, a2, 11
+; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieq a1, a0, a2, 11
+; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a2, a1, a0, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %b, %a
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ne1:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bne a1, a0, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ne1:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectine a1, a0, a2, 11
+; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ne1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectine a1, a0, a2, 11
+; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a2, a1, a0, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %b, %a
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+
+define i32 @select_cc_example_eq2(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a1, a0, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a0, 11
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB23_2:
+; RV32I-NEXT: li a0, 15
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq2:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectiieq a1, a0, 15, 11
+; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectiieq a1, a0, 15, 11
+; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectiieq a1, a0, 15, 11
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %b, %a
+ %sel = select i1 %cmp, i32 15, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ne2(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ne2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bne a1, a0, .LBB24_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a0, 11
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB24_2:
+; RV32I-NEXT: li a0, 15
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ne2:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectiine a1, a0, 15, 11
+; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ne2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectiine a1, a0, 15, 11
+; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectiine a1, a0, 15, 11
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %b, %a
+ %sel = select i1 %cmp, i32 15, i32 11
+ ret i32 %sel
+}
>From 15da9e7cbed2d61eec5b521c3510639a5bf59618 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Mon, 29 Sep 2025 12:32:32 +0530
Subject: [PATCH 3/4] fixup! Update tests
Change-Id: Ief8665a789bd210c50fadb91dabd6ff9f1fbc489
---
llvm/test/CodeGen/RISCV/xqcics.ll | 30 ++++++++++--------------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 80f9c19e7caaf..5c9fd1b82fbf5 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -702,14 +702,12 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICS-LABEL: select_cc_example_eq1:
; RV32IXQCICS: # %bb.0: # %entry
-; RV32IXQCICS-NEXT: qc.selectieq a1, a0, a2, 11
-; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_eq1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.selectieq a1, a0, a2, 11
-; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq1:
@@ -735,14 +733,12 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICS-LABEL: select_cc_example_ne1:
; RV32IXQCICS: # %bb.0: # %entry
-; RV32IXQCICS-NEXT: qc.selectine a1, a0, a2, 11
-; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_ne1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.selectine a1, a0, a2, 11
-; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne1:
@@ -770,20 +766,17 @@ define i32 @select_cc_example_eq2(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICS-LABEL: select_cc_example_eq2:
; RV32IXQCICS: # %bb.0: # %entry
-; RV32IXQCICS-NEXT: qc.selectiieq a1, a0, 15, 11
-; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 15, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_eq2:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.selectiieq a1, a0, 15, 11
-; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: qc.selectiieq a0, a1, 15, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selectiieq a1, a0, 15, 11
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: qc.selectiieq a0, a1, 15, 11
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %a
@@ -804,20 +797,17 @@ define i32 @select_cc_example_ne2(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICS-LABEL: select_cc_example_ne2:
; RV32IXQCICS: # %bb.0: # %entry
-; RV32IXQCICS-NEXT: qc.selectiine a1, a0, 15, 11
-; RV32IXQCICS-NEXT: mv a0, a1
+; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 15, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_ne2:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.selectiine a1, a0, 15, 11
-; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: qc.selectiine a0, a1, 15, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selectiine a1, a0, 15, 11
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: qc.selectiine a0, a1, 15, 11
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %a
>From 7ccb5b28e1cfb4c137e840f994acd06d0a8d2f21 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Tue, 30 Sep 2025 12:46:59 +0530
Subject: [PATCH 4/4] fixup! Remove CloneIfNew
Change-Id: I433db282e271369a94994acada4052bf77fb4343
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 4812fb981085d..30b0ef5200903 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3983,8 +3983,7 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
case RISCV::QC_SELECTINE:
case RISCV::QC_SELECTIIEQ:
case RISCV::QC_SELECTIINE: {
- auto &WorkingMI = cloneIfNew(MI);
- return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1,
OpIdx2);
}
case RISCV::PseudoCCMOVGPRNoX0:
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