[llvm] [Docs][RISCV]Remove experimental from Smctr, Ssctr,Sdext and Sdtrig (PR #161058)

[Liao Chunyu via llvm-commits]

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@@ -306,6 +310,11 @@ Supported
 ``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
   These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__.  They do not introduce any new features themselves, but instead describe existing hardware features.
 
+.. _riscv-extensions-specifications-note:
+
+``Sdext``, ``Sdtrig`` `The RISC-V Debug Specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0/riscv-debug-specification.pdf>`__.
+``Smctr``, ``Ssctr`` `RISC-V Control Transfer Records <https://github.com/riscv/riscv-control-transfer-records/releases/download/v1.0_rc3/riscv-ctr-v1.0_rc3.pdf>`__.
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ChunyuLiao wrote:

delete Smctr and Ssctr spec.

https://github.com/llvm/llvm-project/pull/161058