[llvm] 46ea039 - [RISCV] Add commutative support for Qualcomm uC Xqcicm extension (#160653)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 29 22:14:41 PDT 2025
Author: quic_hchandel
Date: 2025-09-30T10:44:37+05:30
New Revision: 46ea03997da6b07dda451be7e15ec7f13ebbe3ea
URL: https://github.com/llvm/llvm-project/commit/46ea03997da6b07dda451be7e15ec7f13ebbe3ea
DIFF: https://github.com/llvm/llvm-project/commit/46ea03997da6b07dda451be7e15ec7f13ebbe3ea.diff
LOG: [RISCV] Add commutative support for Qualcomm uC Xqcicm extension (#160653)
This is a follow-up to #145643. See
https://github.com/llvm/llvm-project/pull/145643#issuecomment-3009300419.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
llvm/test/CodeGen/RISCV/select-bare.ll
llvm/test/CodeGen/RISCV/select-cc.ll
llvm/test/CodeGen/RISCV/select-cond.ll
llvm/test/CodeGen/RISCV/select.ll
llvm/test/CodeGen/RISCV/xqcicm.ll
llvm/test/CodeGen/RISCV/xqcics.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6d418fda82534..70b6c7ea35f82 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1023,6 +1023,37 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
+static unsigned getInverseXqcicmOpcode(unsigned Opcode) {
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected Opcode");
+ case RISCV::QC_MVEQ:
+ return RISCV::QC_MVNE;
+ case RISCV::QC_MVNE:
+ return RISCV::QC_MVEQ;
+ case RISCV::QC_MVLT:
+ return RISCV::QC_MVGE;
+ case RISCV::QC_MVGE:
+ return RISCV::QC_MVLT;
+ case RISCV::QC_MVLTU:
+ return RISCV::QC_MVGEU;
+ case RISCV::QC_MVGEU:
+ return RISCV::QC_MVLTU;
+ case RISCV::QC_MVEQI:
+ return RISCV::QC_MVNEI;
+ case RISCV::QC_MVNEI:
+ return RISCV::QC_MVEQI;
+ case RISCV::QC_MVLTI:
+ return RISCV::QC_MVGEI;
+ case RISCV::QC_MVGEI:
+ return RISCV::QC_MVLTI;
+ case RISCV::QC_MVLTUI:
+ return RISCV::QC_MVGEUI;
+ case RISCV::QC_MVGEUI:
+ return RISCV::QC_MVLTUI;
+ }
+}
+
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
switch (SelectOpc) {
default:
@@ -3762,6 +3793,19 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
return false;
// Operands 1 and 2 are commutable, if we switch the opcode.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
+ case RISCV::QC_MVEQ:
+ case RISCV::QC_MVNE:
+ case RISCV::QC_MVLT:
+ case RISCV::QC_MVGE:
+ case RISCV::QC_MVLTU:
+ case RISCV::QC_MVGEU:
+ case RISCV::QC_MVEQI:
+ case RISCV::QC_MVNEI:
+ case RISCV::QC_MVLTI:
+ case RISCV::QC_MVGEI:
+ case RISCV::QC_MVLTUI:
+ case RISCV::QC_MVGEUI:
+ return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 4);
case RISCV::TH_MULA:
case RISCV::TH_MULAW:
case RISCV::TH_MULAH:
@@ -3974,6 +4018,23 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
+ case RISCV::QC_MVEQ:
+ case RISCV::QC_MVNE:
+ case RISCV::QC_MVLT:
+ case RISCV::QC_MVGE:
+ case RISCV::QC_MVLTU:
+ case RISCV::QC_MVGEU:
+ case RISCV::QC_MVEQI:
+ case RISCV::QC_MVNEI:
+ case RISCV::QC_MVLTI:
+ case RISCV::QC_MVGEI:
+ case RISCV::QC_MVLTUI:
+ case RISCV::QC_MVGEUI: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(getInverseXqcicmOpcode(MI.getOpcode())));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
case RISCV::PseudoCCMOVGPRNoX0:
case RISCV::PseudoCCMOVGPR: {
// CCMOV can be commuted by inverting the condition.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 13b02d1b2d6db..ff4a0406799b1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -604,7 +604,7 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes
let Inst{31-25} = {simm, funct2};
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCIMVCC<bits<3> funct3, string opcodestr>
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
@@ -612,7 +612,7 @@ class QCIMVCC<bits<3> funct3, string opcodestr>
let Constraints = "$rd = $rd_wb";
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll
index 796121ac572ce..44028a7651b95 100644
--- a/llvm/test/CodeGen/RISCV/select-bare.ll
+++ b/llvm/test/CodeGen/RISCV/select-bare.ll
@@ -26,8 +26,8 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32IXQCI-LABEL: bare_select:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
@@ -53,8 +53,8 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32IXQCI-LABEL: bare_select_float:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 14055dff40d42..b57f625cb867f 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -87,40 +87,40 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
;
; RV32IXQCI-LABEL: foo:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: lw a5, 0(a1)
; RV32IXQCI-NEXT: lw a2, 0(a1)
; RV32IXQCI-NEXT: lw a4, 0(a1)
; RV32IXQCI-NEXT: lw t5, 0(a1)
; RV32IXQCI-NEXT: lw t4, 0(a1)
+; RV32IXQCI-NEXT: lw t3, 0(a1)
; RV32IXQCI-NEXT: lw t2, 0(a1)
-; RV32IXQCI-NEXT: lw t1, 0(a1)
; RV32IXQCI-NEXT: lw t0, 0(a1)
; RV32IXQCI-NEXT: lw a7, 0(a1)
; RV32IXQCI-NEXT: lw a6, 0(a1)
-; RV32IXQCI-NEXT: lw t3, 0(a1)
; RV32IXQCI-NEXT: lw a3, 0(a1)
-; RV32IXQCI-NEXT: bltz t3, .LBB0_2
+; RV32IXQCI-NEXT: lw t1, 0(a1)
+; RV32IXQCI-NEXT: lw a5, 0(a1)
+; RV32IXQCI-NEXT: bltz t1, .LBB0_2
; RV32IXQCI-NEXT: # %bb.1:
-; RV32IXQCI-NEXT: li t6, 0
-; RV32IXQCI-NEXT: qc.mveq a5, a0, a5, a0
-; RV32IXQCI-NEXT: qc.mvne a2, a5, a2, a5
-; RV32IXQCI-NEXT: qc.mvltu a4, a4, a2, a2
-; RV32IXQCI-NEXT: qc.mvgeu t5, a4, t5, a4
-; RV32IXQCI-NEXT: qc.mvltu t4, t5, t4, t5
-; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t4, t4
-; RV32IXQCI-NEXT: qc.mvlt t1, t1, t2, t2
-; RV32IXQCI-NEXT: qc.mvge t0, t1, t0, t1
-; RV32IXQCI-NEXT: qc.mvlt a7, t0, a7, t0
-; RV32IXQCI-NEXT: qc.mvge a6, a6, a7, a7
-; RV32IXQCI-NEXT: mv a3, t3
-; RV32IXQCI-NEXT: qc.mvge a3, t6, t3, a6
+; RV32IXQCI-NEXT: li a5, 0
+; RV32IXQCI-NEXT: qc.mveq a2, a0, a2, a0
+; RV32IXQCI-NEXT: qc.mvne a4, a2, a4, a2
+; RV32IXQCI-NEXT: qc.mvltu t5, t5, a4, a4
+; RV32IXQCI-NEXT: qc.mvgeu t4, t5, t4, t5
+; RV32IXQCI-NEXT: qc.mvltu t3, t4, t3, t4
+; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t3, t3
+; RV32IXQCI-NEXT: qc.mvlt t0, t0, t2, t2
+; RV32IXQCI-NEXT: qc.mvge a7, t0, a7, t0
+; RV32IXQCI-NEXT: qc.mvlt a6, a7, a6, a7
+; RV32IXQCI-NEXT: qc.mvge a3, a3, a6, a6
+; RV32IXQCI-NEXT: qc.mvlt a3, a5, t1, t1
+; RV32IXQCI-NEXT: mv a5, a3
; RV32IXQCI-NEXT: .LBB0_2:
; RV32IXQCI-NEXT: lw a2, 0(a1)
; RV32IXQCI-NEXT: lw a0, 0(a1)
; RV32IXQCI-NEXT: li a1, 1024
-; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a5
; RV32IXQCI-NEXT: li a1, 2046
-; RV32IXQCI-NEXT: qc.mvltu a0, a1, t3, a2
+; RV32IXQCI-NEXT: qc.mvltu a0, a1, t1, a2
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: foo:
@@ -417,8 +417,8 @@ define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z)
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a3, 1048560
; RV32IXQCI-NEXT: addi a3, a3, -1
-; RV32IXQCI-NEXT: qc.mvlt a2, a3, a0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mvge a1, a3, a0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_sge_int16min:
@@ -471,10 +471,10 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
; RV32IXQCI-NEXT: srli a0, a1, 31
; RV32IXQCI-NEXT: xori a0, a0, 1
; RV32IXQCI-NEXT: qc.mveqi a0, a1, -1, a6
-; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
-; RV32IXQCI-NEXT: qc.mvnei a5, a0, 0, a3
-; RV32IXQCI-NEXT: mv a0, a4
-; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 0, a5
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: mv a1, a3
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_sge_int32min:
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index b88fe9aae18ec..3ca0f46e8c02f 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -35,8 +35,8 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICM-LABEL: select_i32_trunc:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32-XQCICM-NEXT: mv a0, a1
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_trunc:
@@ -48,8 +48,8 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32IXQCI-LABEL: select_i32_trunc:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_trunc:
@@ -93,8 +93,8 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICM-LABEL: select_i32_param:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32-XQCICM-NEXT: mv a0, a1
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_param:
@@ -106,8 +106,8 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32IXQCI-LABEL: select_i32_param:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_param:
@@ -148,8 +148,8 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32-XQCICM-LABEL: select_i32_eq:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mveq a3, a0, a1, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvne a2, a0, a1, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_eq:
@@ -163,8 +163,8 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32IXQCI-LABEL: select_i32_eq:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_eq:
@@ -205,8 +205,8 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32-XQCICM-LABEL: select_i32_ne:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvne a3, a0, a1, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mveq a2, a0, a1, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ne:
@@ -220,8 +220,8 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32IXQCI-LABEL: select_i32_ne:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_ne:
@@ -262,8 +262,8 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_ugt:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvltu a3, a1, a0, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvgeu a2, a1, a0, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ugt:
@@ -277,8 +277,8 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_ugt:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_ugt:
@@ -319,8 +319,8 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_uge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_uge:
@@ -334,8 +334,8 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_uge:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_uge:
@@ -376,8 +376,8 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_ult:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ult:
@@ -391,8 +391,8 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_ult:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_ult:
@@ -433,8 +433,8 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_ule:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ule:
@@ -448,8 +448,8 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_ule:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_ule:
@@ -490,8 +490,8 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sgt:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvlt a3, a1, a0, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvge a2, a1, a0, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sgt:
@@ -505,8 +505,8 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_sgt:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_sgt:
@@ -547,8 +547,8 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvge a3, a0, a1, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sge:
@@ -562,8 +562,8 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_sge:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_sge:
@@ -604,8 +604,8 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_slt:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvge a2, a0, a1, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_slt:
@@ -619,8 +619,8 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_slt:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_slt:
@@ -661,8 +661,8 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sle:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvge a3, a1, a0, a2
-; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sle:
@@ -676,8 +676,8 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32IXQCI-LABEL: select_i32_sle:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_sle:
@@ -723,11 +723,11 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICM-LABEL: select_i64_trunc:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a3
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a2
-; RV32-XQCICM-NEXT: qc.mvnei a1, a0, 0, a3
-; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_trunc:
@@ -740,11 +740,11 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
;
; RV32IXQCI-LABEL: select_i64_trunc:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: mv a1, a3
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
-; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a3
-; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a5
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_trunc:
@@ -792,10 +792,10 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-LABEL: select_i64_param:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mvnei a3, a0, 0, a1
-; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a2
-; RV32-XQCICM-NEXT: mv a0, a3
-; RV32-XQCICM-NEXT: mv a1, a4
+; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a3
+; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4
+; RV32-XQCICM-NEXT: mv a0, a1
+; RV32-XQCICM-NEXT: mv a1, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_param:
@@ -810,10 +810,10 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32IXQCI-LABEL: select_i64_param:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 0, a1
-; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a3
-; RV32IXQCI-NEXT: mv a1, a4
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: mv a1, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_param:
@@ -866,10 +866,10 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: xor a1, a1, a3
; RV32-XQCICM-NEXT: xor a0, a0, a2
; RV32-XQCICM-NEXT: or a0, a0, a1
-; RV32-XQCICM-NEXT: qc.mveqi a6, a0, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a0, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a6
+; RV32-XQCICM-NEXT: qc.mvnei a5, a0, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_eq:
@@ -887,10 +887,10 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: xor a1, a1, a3
; RV32IXQCI-NEXT: xor a0, a0, a2
; RV32IXQCI-NEXT: or a0, a0, a1
-; RV32IXQCI-NEXT: qc.mveqi a6, a0, 0, a4
-; RV32IXQCI-NEXT: qc.mveqi a7, a0, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a6
+; RV32IXQCI-NEXT: qc.mvnei a5, a0, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_eq:
@@ -943,10 +943,10 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: xor a1, a1, a3
; RV32-XQCICM-NEXT: xor a0, a0, a2
; RV32-XQCICM-NEXT: or a0, a0, a1
-; RV32-XQCICM-NEXT: qc.mvnei a6, a0, 0, a4
-; RV32-XQCICM-NEXT: qc.mvnei a7, a0, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mveqi a4, a0, 0, a6
+; RV32-XQCICM-NEXT: qc.mveqi a5, a0, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ne:
@@ -964,10 +964,10 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: xor a1, a1, a3
; RV32IXQCI-NEXT: xor a0, a0, a2
; RV32IXQCI-NEXT: or a0, a0, a1
-; RV32IXQCI-NEXT: qc.mvnei a6, a0, 0, a4
-; RV32IXQCI-NEXT: qc.mvnei a7, a0, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mveqi a4, a0, 0, a6
+; RV32IXQCI-NEXT: qc.mveqi a5, a0, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ne:
@@ -1025,10 +1025,10 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ugt:
@@ -1050,10 +1050,10 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: sltu a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ugt:
@@ -1111,10 +1111,10 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_uge:
@@ -1136,10 +1136,10 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: sltu a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_uge:
@@ -1197,10 +1197,10 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ult:
@@ -1222,10 +1222,10 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: sltu a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ult:
@@ -1283,10 +1283,10 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ule:
@@ -1308,10 +1308,10 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: sltu a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ule:
@@ -1369,10 +1369,10 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sgt:
@@ -1394,10 +1394,10 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: slt a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_sgt:
@@ -1455,10 +1455,10 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sge:
@@ -1480,10 +1480,10 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: slt a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_sge:
@@ -1541,10 +1541,10 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_slt:
@@ -1566,10 +1566,10 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: slt a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_slt:
@@ -1627,10 +1627,10 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sle:
@@ -1652,10 +1652,10 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: slt a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
-; RV32IXQCI-NEXT: mv a0, a6
-; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a6
+; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a7
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_sle:
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 19fade67afc3d..8273c65bf512e 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -1153,8 +1153,8 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_sub_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: sub a1, a1, a2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
@@ -1301,9 +1301,9 @@ define i32 @select_sub_4(i1 zeroext %cond, i32 %x) {
;
; RV32IXQCI-LABEL: select_sub_4:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: addi a1, a1, -128
-; RV32IXQCI-NEXT: li a2, 128
-; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: addi a2, a1, -128
+; RV32IXQCI-NEXT: li a1, 128
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%add = sub i32 %x, 128
@@ -1348,8 +1348,8 @@ define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_and_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: and a1, a1, a2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
@@ -1493,8 +1493,8 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_udiv_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: divu a1, a1, a2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
@@ -1682,8 +1682,8 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_shl_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: sll a1, a1, a2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
@@ -1798,8 +1798,8 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_ashr_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: sra a1, a1, a2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
@@ -1914,8 +1914,8 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_lshr_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: srl a1, a1, a2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
@@ -2371,9 +2371,9 @@ define i32 @select_cst5(i1 zeroext %cond) {
; RV32IXQCI-LABEL: select_cst5:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a1, 1
-; RV32IXQCI-NEXT: addi a1, a1, -2047
-; RV32IXQCI-NEXT: li a2, 2047
-; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: addi a2, a1, -2047
+; RV32IXQCI-NEXT: li a1, 2047
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2047, i32 2049
@@ -2870,8 +2870,8 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
-; RV32IXQCI-NEXT: qc.mveqi a0, a0, 0, a2
-; RV32IXQCI-NEXT: sw a0, 0(a1)
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a0
+; RV32IXQCI-NEXT: sw a2, 0(a1)
; RV32IXQCI-NEXT: ret
entry:
%3 = icmp eq ptr %0, null
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 1741be742323d..fb48301b1d8e8 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -23,15 +23,15 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32IXQCICM-LABEL: select_example:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: andi a0, a0, 1
-; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCICM-NEXT: mv a0, a1
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_example:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
@@ -52,14 +52,14 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
@@ -80,14 +80,14 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
@@ -108,14 +108,14 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
@@ -136,14 +136,14 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
@@ -164,14 +164,14 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, 11
@@ -192,14 +192,14 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 11, %a
@@ -220,14 +220,14 @@ define i32 @select_cc_example_sle(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, 11
@@ -248,14 +248,14 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 11, %a
@@ -276,14 +276,14 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 11
@@ -304,14 +304,14 @@ define i32 @select_cc_example_sgt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 11, %a
@@ -332,14 +332,14 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, 11
@@ -360,14 +360,14 @@ define i32 @select_cc_example_sge1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 11, %a
@@ -388,14 +388,14 @@ define i32 @select_cc_example_ule(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, 11
@@ -416,14 +416,14 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 11, %a
@@ -444,14 +444,14 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, 11
@@ -472,14 +472,14 @@ define i32 @select_cc_example_ugt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 11, %a
@@ -500,14 +500,14 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, 11
@@ -528,14 +528,14 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 11, %a
@@ -556,14 +556,14 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, 11
@@ -584,14 +584,14 @@ define i32 @select_cc_example_uge1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 11, %a
@@ -611,14 +611,14 @@ define i32 @select_cc_example_eq_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
@@ -638,14 +638,14 @@ define i32 @select_cc_example_ne_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
@@ -665,14 +665,14 @@ define i32 @select_cc_example_slt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, %b
@@ -692,14 +692,14 @@ define i32 @select_cc_example_sge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvge a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, %b
@@ -719,14 +719,14 @@ define i32 @select_cc_example_sgt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvge a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, %b
@@ -746,14 +746,14 @@ define i32 @select_cc_example_sle_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvge a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, %b
@@ -773,14 +773,14 @@ define i32 @select_cc_example_ugt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, %b
@@ -800,14 +800,14 @@ define i32 @select_cc_example_ult_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, %b
@@ -827,14 +827,14 @@ define i32 @select_cc_example_uge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, %b
@@ -854,14 +854,14 @@ define i32 @select_cc_example_ule_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, %b
@@ -883,18 +883,263 @@ define i32 @select_cc_example_ule_neg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-LABEL: select_cc_example_ule_neg:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: li a1, -10
-; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule_neg:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: li a1, -10
-; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, -11
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
+
+define i32 @select_cc_example_eq_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a2, a1, .LBB32_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvne a0, a2, a1, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvne a0, a2, a1, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_lt_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_lt_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: blt a2, a1, .LBB33_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_lt_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvge a0, a2, a1, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_lt_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvge a0, a2, a1, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp slt i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ge_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ge_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bge a2, a1, .LBB34_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB34_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ge_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvlt a0, a2, a1, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ge_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlt a0, a2, a1, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp sge i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ult_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ult_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bltu a2, a1, .LBB35_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB35_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ult_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvgeu a0, a2, a1, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeu a0, a2, a1, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp ult i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_uge_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_uge_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bgeu a2, a1, .LBB36_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB36_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_uge_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvltu a0, a2, a1, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltu a0, a2, a1, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp uge i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_eq_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: beq a2, a1, .LBB37_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB37_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvnei a0, a2, 11, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvnei a0, a2, 11, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_lt_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_lt_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: blt a2, a1, .LBB38_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB38_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_lt_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvgei a0, a2, 11, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_lt_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a0, a2, 11, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp slt i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ge_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ge_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 10
+; RV32I-NEXT: blt a1, a2, .LBB39_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB39_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ge_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvlti a0, a2, 11, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ge_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a0, a2, 11, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp sge i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ult_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ult_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: bltu a2, a1, .LBB40_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB40_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ult_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvgeui a0, a2, 11, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a0, a2, 11, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp ult i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_uge_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_uge_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 10
+; RV32I-NEXT: bltu a1, a2, .LBB41_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB41_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_uge_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvltui a0, a2, 11, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a0, a2, 11, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp uge i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 38de8fbd78b36..5b7ca9e7fedb8 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -134,14 +134,14 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
@@ -167,14 +167,14 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq_c:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq_c:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
@@ -200,14 +200,14 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
@@ -233,14 +233,14 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne_c:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne_c:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
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