[llvm] [DAGCombiner] Remove most `NoSignedZerosFPMath` uses (PR #161180)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 29 18:47:40 PDT 2025
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/161180
>From 0891cc1fbbf9988b94a2b1e86fbf75db8b81ee3c Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Mon, 29 Sep 2025 19:22:45 +0800
Subject: [PATCH 1/2] [DAGCombiner] Remove most `NoSignedZerosFPMath` uses
Remained two uses are related to fneg and foldFPToIntToFP
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 77df4b4598c48..204e1f0c75e00 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11849,9 +11849,7 @@ static bool isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS,
if (!VT.isFloatingPoint())
return false;
- const TargetOptions &Options = DAG.getTarget().Options;
-
- return (Flags.hasNoSignedZeros() || Options.NoSignedZerosFPMath) &&
+ return Flags.hasNoSignedZeros() &&
TLI.isProfitableToCombineMinNumMaxNum(VT) &&
(Flags.hasNoNaNs() ||
(DAG.isKnownNeverNaN(RHS) && DAG.isKnownNeverNaN(LHS)));
@@ -17351,7 +17349,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
// Always prefer FMAD to FMA for precision.
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
- bool NoSignedZero = Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros();
+ bool NoSignedZero = Flags.hasNoSignedZeros();
// Is the node an FMUL and contractable either due to global flags or
// SDNodeFlags.
@@ -18327,11 +18325,9 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
return matcher.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2);
}
- // FIXME: use fast math flags instead of Options.UnsafeFPMath
- // TODO: Finally migrate away from global TargetOptions.
if ((Options.NoNaNsFPMath && Options.NoInfsFPMath) ||
(N->getFlags().hasNoNaNs() && N->getFlags().hasNoInfs())) {
- if (Options.NoSignedZerosFPMath || N->getFlags().hasNoSignedZeros() ||
+ if (N->getFlags().hasNoSignedZeros() ||
(N2CFP && !N2CFP->isExactlyValue(-0.0))) {
if (N0CFP && N0CFP->isZero())
return N2;
@@ -18636,8 +18632,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
}
// Fold X/Sqrt(X) -> Sqrt(X)
- if ((Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) &&
- Flags.hasAllowReassociation())
+ if (Flags.hasNoSignedZeros() && Flags.hasAllowReassociation())
if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
return N1;
>From 985465638cc7e21df166dae7103fb64cef7f8b0b Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Tue, 30 Sep 2025 09:47:23 +0800
Subject: [PATCH 2/2] fix tests
---
llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll | 1421 +++++++++--------
llvm/test/CodeGen/AMDGPU/fmax_legacy.ll | 226 ++-
.../CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll | 281 +++-
llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll | 1421 +++++++++--------
llvm/test/CodeGen/AMDGPU/fmin_legacy.ll | 302 +++-
llvm/test/CodeGen/NVPTX/bug22322.ll | 6 +-
llvm/test/CodeGen/PowerPC/scalar-min-max.ll | 232 ++-
llvm/test/CodeGen/VE/Scalar/max.ll | 176 +-
llvm/test/CodeGen/VE/Scalar/min.ll | 178 +--
9 files changed, 2306 insertions(+), 1937 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
index ed48999e6d1e7..bd28f72bb8913 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
@@ -1,734 +1,759 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-NNAN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-NNAN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI %s
-; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefixes=SI-NNAN %s
+; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SAFE-TRUE16 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SAFE-FAKE16 %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-NNAN,GFX11-NNAN-TRUE16 %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-NNAN,GFX11-NNAN-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
define half @test_fmax_legacy_ugt_f16(half %a, half %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v1, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v1
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-TRUE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-NNAN-TRUE16: ; %bb.0:
-; GFX11-NNAN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NNAN-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-FAKE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-NNAN-FAKE16: ; %bb.0:
-; GFX11-NNAN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11-NNAN-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_max_legacy_f32_e32 v0, v1, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ugt half %a, %b
%val = select i1 %cmp, half %a, half %b
ret half %val
}
+define half @test_fmax_legacy_ugt_f16_fast(half %a, half %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_max_f16_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_max_f32_e32 v0, v0, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_f16_fast:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_f16_fast:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ugt half %a, %b
+ %val = select nnan nsz i1 %cmp, half %a, half %b
+ ret half %val
+}
+
define <2 x half> @test_fmax_legacy_ugt_v2f16(<2 x half> %a, <2 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2
-; VI-SAFE-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v3, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v2
-; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v3
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v2
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v2f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2
+; VI-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v2f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_max_legacy_f32_e32 v0, v2, v0
+; SI-NEXT: v_max_legacy_f32_e32 v1, v3, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v2f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v2f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ugt <2 x half> %a, %b
%val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
ret <2 x half> %val
}
+define <2 x half> @test_fmax_legacy_ugt_v2f16_fast(<2 x half> %a, <2 x half> %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_max_f32_e32 v0, v0, v2
+; SI-NEXT: v_max_f32_e32 v1, v1, v3
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ugt <2 x half> %a, %b
+ %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
+ ret <2 x half> %val
+}
+
define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
-; VI-SAFE-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
-; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v4
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v3, v0
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v4, v1
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v2, v5, v2
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v3
-; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v4
-; SI-NNAN-NEXT: v_max_f32_e32 v2, v2, v5
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_v3f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v2.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v1.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_v3f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v5, v4
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v3
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX11-NNAN-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_v3f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v3f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v3f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_max_legacy_f32_e32 v0, v3, v0
+; SI-NEXT: v_max_legacy_f32_e32 v1, v4, v1
+; SI-NEXT: v_max_legacy_f32_e32 v2, v5, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v3f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v3f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ugt <3 x half> %a, %b
%val = select <3 x i1> %cmp, <3 x half> %a, <3 x half> %b
ret <3 x half> %val
}
+define <3 x half> @test_fmax_legacy_ugt_v3f16_fast(<3 x half> %a, <3 x half> %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_v3f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v3f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_e32 v0, v0, v2
+; VI-NEXT: v_max_f16_e32 v1, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v4
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v3f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_max_f32_e32 v0, v0, v3
+; SI-NEXT: v_max_f32_e32 v1, v1, v4
+; SI-NEXT: v_max_f32_e32 v2, v2, v5
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmax_legacy_ugt_v3f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-NEXT: v_pk_max_f16 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ugt <3 x half> %a, %b
+ %val = select nnan nsz <3 x i1> %cmp, <3 x half> %a, <3 x half> %b
+ ret <3 x half> %val
+}
+
define <4 x half> @test_fmax_legacy_ugt_v4f16(<4 x half> %a, <4 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v1, v6, v1, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; VI-SAFE-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
-; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v5
-; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v4
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v4, v0
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v5, v1
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v2, v6, v2
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v3, v7, v3
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v4
-; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v5
-; SI-NNAN-NEXT: v_max_f32_e32 v2, v2, v6
-; SI-NNAN-NEXT: v_max_f32_e32 v3, v3, v7
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_v4f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v3.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.h, v2.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v0.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v1.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_v4f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v5, v4
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v7, v6
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v3
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX11-NNAN-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_v4f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
+; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v4f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v4
+; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v4f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_max_legacy_f32_e32 v0, v4, v0
+; SI-NEXT: v_max_legacy_f32_e32 v1, v5, v1
+; SI-NEXT: v_max_legacy_f32_e32 v2, v6, v2
+; SI-NEXT: v_max_legacy_f32_e32 v3, v7, v3
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v4f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v4f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v7, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ugt <4 x half> %a, %b
%val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
ret <4 x half> %val
}
+define <4 x half> @test_fmax_legacy_ugt_v4f16_fast(<4 x half> %a, <4 x half> %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_v4f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v4f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_e32 v1, v1, v3
+; VI-NEXT: v_max_f16_e32 v0, v0, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v4f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_max_f32_e32 v0, v0, v4
+; SI-NEXT: v_max_f32_e32 v1, v1, v5
+; SI-NEXT: v_max_f32_e32 v2, v2, v6
+; SI-NEXT: v_max_f32_e32 v3, v3, v7
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmax_legacy_ugt_v4f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_max_f16 v0, v0, v2
+; GFX11-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ugt <4 x half> %a, %b
+ %val = select nnan nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
+ ret <4 x half> %val
+}
+
define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v8, v0, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v1, v10, v1, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v2, v12, v2, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v3, v14, v3, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v4
-; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v5
-; GFX9-NNAN-NEXT: v_pk_max_f16 v2, v2, v6
-; GFX9-NNAN-NEXT: v_pk_max_f16 v3, v3, v7
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v10
-; VI-SAFE-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v12
-; VI-SAFE-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v14
-; VI-SAFE-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_max_f16_e32 v3, v3, v7
-; VI-NNAN-NEXT: v_max_f16_e32 v2, v2, v6
-; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v5
-; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v4
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v11
-; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v10
-; VI-NNAN-NEXT: v_or_b32_e32 v2, v2, v9
-; VI-NNAN-NEXT: v_or_b32_e32 v3, v3, v8
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v13, v13
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v12, v12
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v11, v11
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v10, v10
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v9, v9
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v15, v15
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v14, v14
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v13, v13
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v12, v12
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v11, v11
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v10, v10
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v8, v0
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v9, v1
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v2, v10, v2
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v3, v11, v3
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v4, v12, v4
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v5, v13, v5
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v6, v14, v6
-; SI-SAFE-NEXT: v_max_legacy_f32_e32 v7, v15, v7
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v15, v15
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v13, v13
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v12, v12
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v11, v11
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v10, v10
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v9, v9
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v15, v15
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v14, v14
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v13, v13
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v12, v12
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v11, v11
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v10, v10
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v8
-; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v9
-; SI-NNAN-NEXT: v_max_f32_e32 v2, v2, v10
-; SI-NNAN-NEXT: v_max_f32_e32 v3, v3, v11
-; SI-NNAN-NEXT: v_max_f32_e32 v4, v4, v12
-; SI-NNAN-NEXT: v_max_f32_e32 v5, v5, v13
-; SI-NNAN-NEXT: v_max_f32_e32 v6, v6, v14
-; SI-NNAN-NEXT: v_max_f32_e32 v7, v7, v15
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_v8f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v4.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v1.h, v5.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v2.h, v6.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v3.h, v7.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s3, v0.l, v4.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s4, v1.l, v5.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s5, v2.l, v6.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_nle_f16_e64 s6, v3.l, v7.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s1
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_v8f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v11, v10
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v13, v12
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v15, v14
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v9, v8
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v2, v6
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v4
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v5
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v7
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_max_f16 v0, v0, v4
-; GFX11-NNAN-NEXT: v_pk_max_f16 v1, v1, v5
-; GFX11-NNAN-NEXT: v_pk_max_f16 v2, v2, v6
-; GFX11-NNAN-NEXT: v_pk_max_f16 v3, v3, v7
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_v8f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v8, v0, s4
+; GFX9-NEXT: v_perm_b32 v1, v10, v1, s4
+; GFX9-NEXT: v_perm_b32 v2, v12, v2, s4
+; GFX9-NEXT: v_perm_b32 v3, v14, v3, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v8f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; VI-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; VI-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10
+; VI-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6
+; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5
+; VI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
+; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v10
+; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; VI-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v8f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_max_legacy_f32_e32 v0, v8, v0
+; SI-NEXT: v_max_legacy_f32_e32 v1, v9, v1
+; SI-NEXT: v_max_legacy_f32_e32 v2, v10, v2
+; SI-NEXT: v_max_legacy_f32_e32 v3, v11, v3
+; SI-NEXT: v_max_legacy_f32_e32 v4, v12, v4
+; SI-NEXT: v_max_legacy_f32_e32 v5, v13, v5
+; SI-NEXT: v_max_legacy_f32_e32 v6, v14, v6
+; SI-NEXT: v_max_legacy_f32_e32 v7, v15, v7
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v8f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v1.h, v5.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v2.h, v6.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v3.h, v7.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s3, v0.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s4, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s5, v2.l, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s6, v3.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v8f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v11, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v13, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v15, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v2, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ugt <8 x half> %a, %b
%val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
ret <8 x half> %val
}
+define <8 x half> @test_fmax_legacy_ugt_v8f16_fast(<8 x half> %a, <8 x half> %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_v8f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v4
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v5
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v6
+; GFX9-NEXT: v_pk_max_f16 v3, v3, v7
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v8f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_max_f16_e32 v3, v3, v7
+; VI-NEXT: v_max_f16_e32 v2, v2, v6
+; VI-NEXT: v_max_f16_e32 v1, v1, v5
+; VI-NEXT: v_max_f16_e32 v0, v0, v4
+; VI-NEXT: v_or_b32_e32 v0, v0, v11
+; VI-NEXT: v_or_b32_e32 v1, v1, v10
+; VI-NEXT: v_or_b32_e32 v2, v2, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v8
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v8f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_max_f32_e32 v0, v0, v8
+; SI-NEXT: v_max_f32_e32 v1, v1, v9
+; SI-NEXT: v_max_f32_e32 v2, v2, v10
+; SI-NEXT: v_max_f32_e32 v3, v3, v11
+; SI-NEXT: v_max_f32_e32 v4, v4, v12
+; SI-NEXT: v_max_f32_e32 v5, v5, v13
+; SI-NEXT: v_max_f32_e32 v6, v6, v14
+; SI-NEXT: v_max_f32_e32 v7, v7, v15
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmax_legacy_ugt_v8f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_max_f16 v0, v0, v4
+; GFX11-NEXT: v_pk_max_f16 v1, v1, v5
+; GFX11-NEXT: v_pk_max_f16 v2, v2, v6
+; GFX11-NEXT: v_pk_max_f16 v3, v3, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ugt <8 x half> %a, %b
+ %val = select nnan nsz <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %val
+}
+
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
index eee2bd1b3725d..f3a84e6e45260 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
@@ -1,8 +1,6 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN,FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN-NONAN,GCN,FUNC %s
+; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN,FUNC %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN,FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=GCN-NONAN,GCN,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,FUNC %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s
@@ -12,12 +10,10 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; VI-SAFE: v_cmp_nlt_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
-
-; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; VI: v_cmp_nlt_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_uge_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
@@ -34,18 +30,38 @@ define amdgpu_kernel void @test_fmax_legacy_uge_f32(ptr addrspace(1) %out, ptr a
ret void
}
+; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_fast:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+
+; EG: MAX
+define amdgpu_kernel void @test_fmax_legacy_uge_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
+
+ %cmp = fcmp uge float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_nnan_src:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]
; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
+; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
-; VI-SAFE: v_cmp_nlt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[ADD_B]], [[ADD_A]]
+; VI: v_cmp_nlt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[ADD_B]], [[ADD_A]]
-; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
@@ -64,16 +80,40 @@ define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src(ptr addrspace(1) %o
ret void
}
+; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_nnan_src_fast:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]
+; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]
+
+; GCN: v_max_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
+
+; EG: MAX
+define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
+ %a.nnan = fadd nnan float %a, 1.0
+ %b.nnan = fadd nnan float %b, 2.0
+
+ %cmp = fcmp uge float %a.nnan, %b.nnan
+ %val = select nnan nsz i1 %cmp, float %a.nnan, float %b.nnan
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmax_legacy_oge_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; VI-SAFE: v_cmp_ge_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+; VI: v_cmp_ge_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
-; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_oge_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
@@ -89,17 +129,35 @@ define amdgpu_kernel void @test_fmax_legacy_oge_f32(ptr addrspace(1) %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32:
+; FUNC-LABEL: {{^}}test_fmax_legacy_oge_f32_fast:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; EG: MAX
+define amdgpu_kernel void @test_fmax_legacy_oge_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
-; VI-SAFE: v_cmp_nle_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+ %cmp = fcmp oge float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+
+; VI: v_cmp_nle_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
-; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_ugt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
@@ -115,16 +173,35 @@ define amdgpu_kernel void @test_fmax_legacy_ugt_f32(ptr addrspace(1) %out, ptr a
ret void
}
+; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32_fast:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; EG: MAX
+define amdgpu_kernel void @test_fmax_legacy_ugt_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
+
+ %cmp = fcmp ugt float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; VI-SAFE: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+; VI: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
-; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_ogt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
@@ -140,17 +217,35 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_f32(ptr addrspace(1) %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32:
+; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32_fast:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; EG: MAX
+define amdgpu_kernel void @test_fmax_legacy_ogt_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
-; VI-SAFE: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+ %cmp = fcmp ogt float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+
+; VI: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
-; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
@@ -166,23 +261,39 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(ptr addrspace(1) %out, ptr
ret void
}
+; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32_fast:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; EG: MAX
+define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr <1 x float>, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile <1 x float>, ptr addrspace(1) %gep.0
+ %b = load volatile <1 x float>, ptr addrspace(1) %gep.1
+
+ %cmp = fcmp ogt <1 x float> %a, %b
+ %val = select nnan nsz <1 x i1> %cmp, <1 x float> %a, <1 x float> %b
+ store <1 x float> %val, ptr addrspace(1) %out
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32:
-; SI-SAFE: v_max_legacy_f32_e32
-; SI-SAFE: v_max_legacy_f32_e32
-; SI-SAFE: v_max_legacy_f32_e32
-
-; VI-SAFE: v_cmp_gt_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE: v_cmp_gt_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE: v_cmp_gt_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE-NOT: v_cmp
-; VI-SAFE-NOT: v_cndmask
-
-; GCN-NONAN: v_max_f32_e32
-; GCN-NONAN: v_max_f32_e32
-; GCN-NONAN: v_max_f32_e32
+; SI: v_max_legacy_f32_e32
+; SI: v_max_legacy_f32_e32
+; SI: v_max_legacy_f32_e32
+
+; VI: v_cmp_gt_f32_e32
+; VI: v_cndmask_b32_e32
+; VI: v_cmp_gt_f32_e32
+; VI: v_cndmask_b32_e32
+; VI: v_cmp_gt_f32_e32
+; VI: v_cndmask_b32_e32
+; VI-NOT: v_cmp
+; VI-NOT: v_cndmask
; GCN-NOT: v_max
define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
@@ -199,6 +310,27 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(ptr addrspace(1) %out, ptr
ret void
}
+; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32_fast:
+
+; GCN: v_max_f32_e32
+; GCN: v_max_f32_e32
+; GCN: v_max_f32_e32
+
+; GCN-NOT: v_max
+define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr <3 x float>, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load <3 x float>, ptr addrspace(1) %gep.0
+ %b = load <3 x float>, ptr addrspace(1) %gep.1
+
+ %cmp = fcmp ogt <3 x float> %a, %b
+ %val = select nnan nsz <3 x i1> %cmp, <3 x float> %a, <3 x float> %b
+ store <3 x float> %val, ptr addrspace(1) %out
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32_multi_use:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll b/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
index 2ac5891773d73..37f077d53cf94 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
@@ -1,16 +1,12 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s
+; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI-NNAN %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN %s
; GCN-LABEL: {{^}}min_fneg_select_regression_0:
; GCN-NOT: v_mul
-; SI: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0
-
-; VI-SAFE: v_cmp_nle_f32_e32 vcc, 1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc
+; VI: v_cmp_nle_f32_e32 vcc, 1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc
define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 {
%fneg.a = fsub float -0.0, %a
%cmp.a = fcmp ult float %a, 1.0
@@ -18,15 +14,23 @@ define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 {
ret float %min.a
}
+; GCN-LABEL: {{^}}min_fneg_select_regression_0_fast:
+; GCN-NOT: v_mul
+
+define amdgpu_ps float @min_fneg_select_regression_0_fast(float %a, float %b) #0 {
+ %fneg.a = fsub float -0.0, %a
+ %cmp.a = fcmp ult float %a, 1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float -1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0:
; GCN-NOT: v_mul
; SI: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0
-; VI-SAFE: v_cmp_nle_f32_e32 vcc, -1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
-
-; VI-NNAN: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.0
+; VI: v_cmp_nle_f32_e32 vcc, -1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0 {
%fneg.a = fsub float -0.0, %a
%cmp.a = fcmp ult float %a, -1.0
@@ -34,15 +38,24 @@ define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0
ret float %min.a
}
-; GCN-LABEL: {{^}}max_fneg_select_regression_0:
+; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0_fast:
; GCN-NOT: v_mul
-; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0
+; VI: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.0
+define amdgpu_ps float @min_fneg_select_regression_posk_0_fast(float %a, float %b) #0 {
+ %fneg.a = fsub float -0.0, %a
+ %cmp.a = fcmp ult float %a, -1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0
+ ret float %min.a
+}
+
+; GCN-LABEL: {{^}}max_fneg_select_regression_0:
+; GCN-NOT: v_mul
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, 1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc
+; SI: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0
-; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.0
+; VI: v_cmp_nge_f32_e32 vcc, 1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc
define amdgpu_ps float @max_fneg_select_regression_0(float %a) #0 {
%fneg.a = fsub float -0.0, %a
%cmp.a = fcmp ugt float %a, 1.0
@@ -50,15 +63,24 @@ define amdgpu_ps float @max_fneg_select_regression_0(float %a) #0 {
ret float %min.a
}
-; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0:
+; GCN-LABEL: {{^}}max_fneg_select_regression_0_fast:
; GCN-NOT: v_mul
-; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0
+; GCN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.0
+define amdgpu_ps float @max_fneg_select_regression_0_fast(float %a) #0 {
+ %fneg.a = fsub float -0.0, %a
+ %cmp.a = fcmp ugt float %a, 1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float -1.0
+ ret float %min.a
+}
+
+; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0:
+; GCN-NOT: v_mul
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, -1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
+; SI: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0
-; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.0
+; VI: v_cmp_nge_f32_e32 vcc, -1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a) #0 {
%fneg.a = fsub float -0.0, %a
%cmp.a = fcmp ugt float %a, -1.0
@@ -66,13 +88,22 @@ define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a) #0 {
ret float %min.a
}
+; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0_fast:
+; GCN-NOT: v_mul
+
+; GCN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.0
+define amdgpu_ps float @max_fneg_select_regression_posk_0_fast(float %a) #0 {
+ %fneg.a = fsub float -0.0, %a
+ %cmp.a = fcmp ugt float %a, -1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg1:
; SI: v_min_legacy_f32_e64 v0, 1.0, -v0
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, -1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
-
-; VI-NNAN: v_min_f32_e64 v0, -v0, 1.0
+; VI: v_cmp_nge_f32_e32 vcc, -1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg1(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ugt float %a, -1.0
@@ -80,13 +111,21 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg1(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg1_fast:
+
+; VI: v_min_f32_e64 v0, -v0, 1.0
+define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg1_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp ugt float %a, -1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg1:
; SI: v_max_legacy_f32_e64 v0, 1.0, -v0
-; VI-SAFE: v_cmp_nle_f32_e32 vcc, -1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
-
-; VI-NNAN: v_max_f32_e64 v0, -v0, 1.0
+; VI: v_cmp_nle_f32_e32 vcc, -1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg1(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ult float %a, -1.0
@@ -94,13 +133,21 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg1(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg1_fast:
+
+; VI: v_max_f32_e64 v0, -v0, 1.0
+define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg1_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp ult float %a, -1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg1:
; SI: v_min_legacy_f32_e64 v0, -v0, 1.0
-; VI-SAFE: v_cmp_lt_f32_e32 vcc, -1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
-
-; VI-NNAN: v_min_f32_e64 v0, -v0, 1.0
+; VI: v_cmp_lt_f32_e32 vcc, -1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ogt float %a, -1.0
@@ -108,13 +155,21 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg1_fast:
+
+; VI: v_min_f32_e64 v0, -v0, 1.0
+define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp ogt float %a, -1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg1:
; SI: v_max_legacy_f32_e64 v0, -v0, 1.0
-; VI-SAFE: v_cmp_gt_f32_e32 vcc, -1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
-
-; VI-NANN: v_max_f32_e64 v0, -v0, 1.0
+; VI: v_cmp_gt_f32_e32 vcc, -1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp olt float %a, -1.0
@@ -122,17 +177,24 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg1_fast:
+
+; VI-NANN: v_max_f32_e64 v0, -v0, 1.0
+define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp olt float %a, -1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg8:
; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
; SI-NEXT: v_min_legacy_f32_e64 v0, [[K]], -v0
-; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
-; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, [[K0]], v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
-
-; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000
-; VI-NNAN-NEXT: v_min_f32_e64 v0, -v0, [[K]]
+; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
+; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
+; VI: v_cmp_nge_f32_e32 vcc, [[K0]], v0
+; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg8(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ugt float %a, -8.0
@@ -140,17 +202,25 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg8(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg8_fast:
+
+; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
+; VI-NEXT: v_min_f32_e64 v0, -v0, [[K]]
+define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg8_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp ugt float %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg8:
; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
; SI-NEXT: v_max_legacy_f32_e64 v0, [[K]], -v0
-; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
-; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
-; VI-SAFE: v_cmp_nle_f32_e32 vcc, [[K0]], v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
-
-; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000
-; VI-NNAN-NEXT: v_max_f32_e64 v0, -v0, [[K]]
+; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
+; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
+; VI: v_cmp_nle_f32_e32 vcc, [[K0]], v0
+; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg8(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ult float %a, -8.0
@@ -158,17 +228,25 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg8(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg8_fast:
+
+; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
+; VI-NEXT: v_max_f32_e64 v0, -v0, [[K]]
+define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg8_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp ult float %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg8:
; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
; SI-NEXT: v_min_legacy_f32_e64 v0, -v0, [[K]]
-; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
-; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
-; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[K0]], v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
-
-; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000
-; VI-NNAN-NEXT: v_min_f32_e64 v0, -v0, [[K]]
+; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
+; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
+; VI: v_cmp_lt_f32_e32 vcc, [[K0]], v0
+; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg8(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ogt float %a, -8.0
@@ -176,18 +254,26 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg8(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg8_fast:
+
+; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
+; VI-NEXT: v_min_f32_e64 v0, -v0, [[K]]
+define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg8_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp ogt float %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg8:
; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
; SI-NEXT: v_max_legacy_f32_e64 v0, -v0, [[K]]
-; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
-; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
-; VI-SAFE: v_cmp_gt_f32_e32 vcc, [[K0]], v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
-
-; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000
-; VI-NNAN-NEXT: v_max_f32_e64 v0, -v0, [[K]]
+; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000
+; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000
+; VI: v_cmp_gt_f32_e32 vcc, [[K0]], v0
+; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc
define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg8(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp olt float %a, -8.0
@@ -195,13 +281,22 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg8(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg8_fast:
+
+; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
+; VI-NEXT: v_max_f32_e64 v0, -v0, [[K]]
+define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg8_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp olt float %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}select_fneg_a_or_neg1_cmp_olt_a_1:
; SI: v_max_legacy_f32_e64 v0, -v0, -1.0
-; VI-SAFE: v_cmp_gt_f32_e32 vcc, 1.0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc
-
-; VI-NNAN: v_max_f32_e64 v0, -v0, -1.0
+; VI: v_cmp_gt_f32_e32 vcc, 1.0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc
define amdgpu_ps float @select_fneg_a_or_neg1_cmp_olt_a_1(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp olt float %a, 1.0
@@ -209,15 +304,22 @@ define amdgpu_ps float @select_fneg_a_or_neg1_cmp_olt_a_1(float %a, float %b) #0
ret float %min.a
}
+; GCN-LABEL: {{^}}select_fneg_a_or_neg1_cmp_olt_a_1_fast:
+
+; VI: v_max_f32_e64 v0, -v0, -1.0
+define amdgpu_ps float @select_fneg_a_or_neg1_cmp_olt_a_1_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp olt float %a, 1.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float -1.0
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}ult_a_select_fneg_a_b:
; SI: v_cmp_nge_f32_e32 vcc, v0, v1
; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, v0, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
-
-; VI-NNAN: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-NNAN-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
+; VI: v_cmp_nge_f32_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
define amdgpu_ps float @ult_a_select_fneg_a_b(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ult float %a, %b
@@ -225,15 +327,23 @@ define amdgpu_ps float @ult_a_select_fneg_a_b(float %a, float %b) #0 {
ret float %min.a
}
+; GCN-LABEL: {{^}}ult_a_select_fneg_a_b_fast:
+
+; VI: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
+define amdgpu_ps float @ult_a_select_fneg_a_b_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp nnan nsz ult float %a, %b
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float %b
+ ret float %min.a
+}
+
; GCN-LABEL: {{^}}ugt_a_select_fneg_a_b:
; SI: v_cmp_nle_f32_e32 vcc, v0, v1
; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
-; VI-SAFE: v_cmp_nle_f32_e32 vcc, v0, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
-
-; VI-NNAN: v_cmp_gt_f32_e32 vcc, v0, v1
-; VI-NNAN-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
+; VI: v_cmp_nle_f32_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
define amdgpu_ps float @ugt_a_select_fneg_a_b(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp ugt float %a, %b
@@ -241,5 +351,16 @@ define amdgpu_ps float @ugt_a_select_fneg_a_b(float %a, float %b) #0 {
ret float %min.a
}
+; GCN-LABEL: {{^}}ugt_a_select_fneg_a_b_fast:
+
+; VI: v_cmp_gt_f32_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc
+define amdgpu_ps float @ugt_a_select_fneg_a_b_fast(float %a, float %b) #0 {
+ %fneg.a = fneg float %a
+ %cmp.a = fcmp nnan nsz ugt float %a, %b
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float %b
+ ret float %min.a
+}
+
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
index 34cb0b1ba29b7..40c2ec0a39f51 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
@@ -1,735 +1,760 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-NNAN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-NNAN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI %s
-; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefixes=SI-NNAN %s
+; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SAFE-TRUE16 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SAFE-FAKE16 %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-NNAN,GFX11-NNAN-TRUE16 %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-NNAN,GFX11-NNAN-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
define half @test_fmin_legacy_ule_f16(half %a, half %b) #0 {
-; GFX9-SAFE-LABEL: test_fmin_legacy_ule_f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmin_legacy_ule_f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmin_legacy_ule_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmin_legacy_ule_f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v1
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmin_legacy_ule_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v0, v1, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmin_legacy_ule_f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_min_f32_e32 v0, v0, v1
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmin_legacy_ule_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmin_legacy_ule_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-TRUE16-LABEL: test_fmin_legacy_ule_f16:
-; GFX11-NNAN-TRUE16: ; %bb.0:
-; GFX11-NNAN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NNAN-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-FAKE16-LABEL: test_fmin_legacy_ule_f16:
-; GFX11-NNAN-FAKE16: ; %bb.0:
-; GFX11-NNAN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11-NNAN-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmin_legacy_ule_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_min_legacy_f32_e32 v0, v1, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
%val = select i1 %cmp, half %a, half %b
ret half %val
}
+define half @test_fmin_legacy_ule_f16_fast(half %a, half %b) #0 {
+; GFX9-LABEL: test_fmin_legacy_ule_f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_min_f16_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_min_f32_e32 v0, v0, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_f16_fast:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_f16_fast:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ule half %a, %b
+ %val = select nnan nsz i1 %cmp, half %a, half %b
+ ret half %val
+}
+
define <2 x half> @test_fmin_legacy_ule_v2f16(<2 x half> %a, <2 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmin_legacy_ule_v2f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v2f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmin_legacy_ule_v2f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2
-; VI-SAFE-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmin_legacy_ule_v2f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v1
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmin_legacy_ule_v2f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v1, v3, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmin_legacy_ule_v2f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_min_f32_e32 v0, v0, v2
-; SI-NNAN-NEXT: v_min_f32_e32 v1, v1, v3
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmin_legacy_ule_v2f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmin_legacy_ule_v2f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmin_legacy_ule_v2f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmin_legacy_ule_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v2f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2
+; VI-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v2f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_min_legacy_f32_e32 v0, v2, v0
+; SI-NEXT: v_min_legacy_f32_e32 v1, v3, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v2f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v2f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x half> %a, %b
%val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
ret <2 x half> %val
}
+define <2 x half> @test_fmin_legacy_ule_v2f16_fast(<2 x half> %a, <2 x half> %b) #0 {
+; GFX9-LABEL: test_fmin_legacy_ule_v2f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v2f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v2f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_min_f32_e32 v0, v0, v2
+; SI-NEXT: v_min_f32_e32 v1, v1, v3
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmin_legacy_ule_v2f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ule <2 x half> %a, %b
+ %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
+ ret <2 x half> %val
+}
+
define <3 x half> @test_fmin_legacy_ule_v3f16(<3 x half> %a, <3 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmin_legacy_ule_v3f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v3f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX9-NNAN-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmin_legacy_ule_v3f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
-; VI-SAFE-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmin_legacy_ule_v3f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v2
-; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v3
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v4
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmin_legacy_ule_v3f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v0, v3, v0
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v1, v4, v1
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v2, v5, v2
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmin_legacy_ule_v3f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_min_f32_e32 v0, v0, v3
-; SI-NNAN-NEXT: v_min_f32_e32 v1, v1, v4
-; SI-NNAN-NEXT: v_min_f32_e32 v2, v2, v5
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmin_legacy_ule_v3f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v2.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v1.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmin_legacy_ule_v3f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmin_legacy_ule_v3f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX11-NNAN-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmin_legacy_ule_v3f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v3f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v3f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_min_legacy_f32_e32 v0, v3, v0
+; SI-NEXT: v_min_legacy_f32_e32 v1, v4, v1
+; SI-NEXT: v_min_legacy_f32_e32 v2, v5, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v3f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v3f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <3 x half> %a, %b
%val = select <3 x i1> %cmp, <3 x half> %a, <3 x half> %b
ret <3 x half> %val
}
+define <3 x half> @test_fmin_legacy_ule_v3f16_fast(<3 x half> %a, <3 x half> %b) #0 {
+; GFX9-LABEL: test_fmin_legacy_ule_v3f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX9-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX9-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v3f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_e32 v0, v0, v2
+; VI-NEXT: v_min_f16_e32 v1, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v4
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v3f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_min_f32_e32 v0, v0, v3
+; SI-NEXT: v_min_f32_e32 v1, v1, v4
+; SI-NEXT: v_min_f32_e32 v2, v2, v5
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmin_legacy_ule_v3f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ule <3 x half> %a, %b
+ %val = select nnan nsz <3 x i1> %cmp, <3 x half> %a, <3 x half> %b
+ ret <3 x half> %val
+}
+
define <4 x half> @test_fmin_legacy_ule_v4f16(<4 x half> %a, <4 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmin_legacy_ule_v4f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v1, v6, v1, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v4f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX9-NNAN-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmin_legacy_ule_v4f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; VI-SAFE-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmin_legacy_ule_v4f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v3
-; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v2
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v5
-; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v4
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmin_legacy_ule_v4f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v0, v4, v0
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v1, v5, v1
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v2, v6, v2
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v3, v7, v3
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmin_legacy_ule_v4f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_min_f32_e32 v0, v0, v4
-; SI-NNAN-NEXT: v_min_f32_e32 v1, v1, v5
-; SI-NNAN-NEXT: v_min_f32_e32 v2, v2, v6
-; SI-NNAN-NEXT: v_min_f32_e32 v3, v3, v7
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmin_legacy_ule_v4f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmin_legacy_ule_v4f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmin_legacy_ule_v4f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX11-NNAN-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmin_legacy_ule_v4f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
+; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v4f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v4
+; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v4f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_min_legacy_f32_e32 v0, v4, v0
+; SI-NEXT: v_min_legacy_f32_e32 v1, v5, v1
+; SI-NEXT: v_min_legacy_f32_e32 v2, v6, v2
+; SI-NEXT: v_min_legacy_f32_e32 v3, v7, v3
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v4f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v4f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <4 x half> %a, %b
%val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
ret <4 x half> %val
}
+define <4 x half> @test_fmin_legacy_ule_v4f16_fast(<4 x half> %a, <4 x half> %b) #0 {
+; GFX9-LABEL: test_fmin_legacy_ule_v4f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX9-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v4f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_e32 v1, v1, v3
+; VI-NEXT: v_min_f16_e32 v0, v0, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v4f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_min_f32_e32 v0, v0, v4
+; SI-NEXT: v_min_f32_e32 v1, v1, v5
+; SI-NEXT: v_min_f32_e32 v2, v2, v6
+; SI-NEXT: v_min_f32_e32 v3, v3, v7
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmin_legacy_ule_v4f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ule <4 x half> %a, %b
+ %val = select nnan nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
+ ret <4 x half> %val
+}
+
define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
-; GFX9-SAFE: ; %bb.0:
-; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v15, v14
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v13, v12
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v11, v10
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v9, v8
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v7
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v2, v6
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v5
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4
-; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT: v_perm_b32 v0, v8, v0, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v1, v10, v1, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v2, v12, v2, s4
-; GFX9-SAFE-NEXT: v_perm_b32 v3, v14, v3, s4
-; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v8f16:
-; GFX9-NNAN: ; %bb.0:
-; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT: v_pk_min_f16 v0, v0, v4
-; GFX9-NNAN-NEXT: v_pk_min_f16 v1, v1, v5
-; GFX9-NNAN-NEXT: v_pk_min_f16 v2, v2, v6
-; GFX9-NNAN-NEXT: v_pk_min_f16 v3, v3, v7
-; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v15, v14
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v13, v12
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v11, v10
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v9, v8
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v7
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v2, v6
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v5
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v10
-; VI-SAFE-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v12
-; VI-SAFE-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v14
-; VI-SAFE-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmin_legacy_ule_v8f16:
-; VI-NNAN: ; %bb.0:
-; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT: v_min_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT: v_min_f16_e32 v3, v3, v7
-; VI-NNAN-NEXT: v_min_f16_e32 v2, v2, v6
-; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v5
-; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v4
-; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v11
-; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v10
-; VI-NNAN-NEXT: v_or_b32_e32 v2, v2, v9
-; VI-NNAN-NEXT: v_or_b32_e32 v3, v3, v8
-; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v13, v13
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v12, v12
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v11, v11
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v10, v10
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v9, v9
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v15, v15
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v14, v14
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v13, v13
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v12, v12
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v11, v11
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v10, v10
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v0, v8, v0
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v1, v9, v1
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v2, v10, v2
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v3, v11, v3
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v4, v12, v4
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v5, v13, v5
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v6, v14, v6
-; SI-SAFE-NEXT: v_min_legacy_f32_e32 v7, v15, v7
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmin_legacy_ule_v8f16:
-; SI-NNAN: ; %bb.0:
-; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v15, v15
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v13, v13
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v12, v12
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v11, v11
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v10, v10
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v9, v9
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v15, v15
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v14, v14
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v13, v13
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v12, v12
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v11, v11
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v10, v10
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT: v_min_f32_e32 v0, v0, v8
-; SI-NNAN-NEXT: v_min_f32_e32 v1, v1, v9
-; SI-NNAN-NEXT: v_min_f32_e32 v2, v2, v10
-; SI-NNAN-NEXT: v_min_f32_e32 v3, v3, v11
-; SI-NNAN-NEXT: v_min_f32_e32 v4, v4, v12
-; SI-NNAN-NEXT: v_min_f32_e32 v5, v5, v13
-; SI-NNAN-NEXT: v_min_f32_e32 v6, v6, v14
-; SI-NNAN-NEXT: v_min_f32_e32 v7, v7, v15
-; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmin_legacy_ule_v8f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v4.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v1.h, v5.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v2.h, v6.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v3.h, v7.h
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s3, v0.l, v4.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s4, v1.l, v5.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s5, v2.l, v6.l
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e64 s6, v3.l, v7.l
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s1
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmin_legacy_ule_v8f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v11, v10
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v13, v12
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v15, v14
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v9, v8
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v2, v6
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v4
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v5
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v7
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmin_legacy_ule_v8f16:
-; GFX11-NNAN: ; %bb.0:
-; GFX11-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT: v_pk_min_f16 v0, v0, v4
-; GFX11-NNAN-NEXT: v_pk_min_f16 v1, v1, v5
-; GFX11-NNAN-NEXT: v_pk_min_f16 v2, v2, v6
-; GFX11-NNAN-NEXT: v_pk_min_f16 v3, v3, v7
-; GFX11-NNAN-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmin_legacy_ule_v8f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v15, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v13, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v11, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v9, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v2, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v8, v0, s4
+; GFX9-NEXT: v_perm_b32 v1, v10, v1, s4
+; GFX9-NEXT: v_perm_b32 v2, v12, v2, s4
+; GFX9-NEXT: v_perm_b32 v3, v14, v3, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v8f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v15, v14
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; VI-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v13, v12
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; VI-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v11, v10
+; VI-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v9, v8
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v7
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v2, v6
+; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v5
+; VI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4
+; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v10
+; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; VI-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v8f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_min_legacy_f32_e32 v0, v8, v0
+; SI-NEXT: v_min_legacy_f32_e32 v1, v9, v1
+; SI-NEXT: v_min_legacy_f32_e32 v2, v10, v2
+; SI-NEXT: v_min_legacy_f32_e32 v3, v11, v3
+; SI-NEXT: v_min_legacy_f32_e32 v4, v12, v4
+; SI-NEXT: v_min_legacy_f32_e32 v5, v13, v5
+; SI-NEXT: v_min_legacy_f32_e32 v6, v14, v6
+; SI-NEXT: v_min_legacy_f32_e32 v7, v15, v7
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v8f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v1.h, v5.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v2.h, v6.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v3.h, v7.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s3, v0.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s4, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s5, v2.l, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s6, v3.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v8f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v11, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v13, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v15, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v2, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <8 x half> %a, %b
%val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
ret <8 x half> %val
}
+define <8 x half> @test_fmin_legacy_ule_v8f16_fast(<8 x half> %a, <8 x half> %b) #0 {
+; GFX9-LABEL: test_fmin_legacy_ule_v8f16_fast:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_min_f16 v0, v0, v4
+; GFX9-NEXT: v_pk_min_f16 v1, v1, v5
+; GFX9-NEXT: v_pk_min_f16 v2, v2, v6
+; GFX9-NEXT: v_pk_min_f16 v3, v3, v7
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmin_legacy_ule_v8f16_fast:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_min_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_min_f16_e32 v3, v3, v7
+; VI-NEXT: v_min_f16_e32 v2, v2, v6
+; VI-NEXT: v_min_f16_e32 v1, v1, v5
+; VI-NEXT: v_min_f16_e32 v0, v0, v4
+; VI-NEXT: v_or_b32_e32 v0, v0, v11
+; VI-NEXT: v_or_b32_e32 v1, v1, v10
+; VI-NEXT: v_or_b32_e32 v2, v2, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v8
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmin_legacy_ule_v8f16_fast:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_min_f32_e32 v0, v0, v8
+; SI-NEXT: v_min_f32_e32 v1, v1, v9
+; SI-NEXT: v_min_f32_e32 v2, v2, v10
+; SI-NEXT: v_min_f32_e32 v3, v3, v11
+; SI-NEXT: v_min_f32_e32 v4, v4, v12
+; SI-NEXT: v_min_f32_e32 v5, v5, v13
+; SI-NEXT: v_min_f32_e32 v6, v6, v14
+; SI-NEXT: v_min_f32_e32 v7, v7, v15
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmin_legacy_ule_v8f16_fast:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_min_f16 v0, v0, v4
+; GFX11-NEXT: v_pk_min_f16 v1, v1, v5
+; GFX11-NEXT: v_pk_min_f16 v2, v2, v6
+; GFX11-NEXT: v_pk_min_f16 v3, v3, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = fcmp ule <8 x half> %a, %b
+ %val = select nnan nsz <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %val
+}
+
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
index ec4dd858b92ea..defcffa641e64 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
@@ -1,8 +1,6 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN,FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI-NONAN,GCN-NONAN,GCN,FUNC %s
+; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN,FUNC %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN,FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-NONAN,GCN-NONAN,GCN,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,FUNC %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s
@@ -14,13 +12,9 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32:
; EG: MIN *
-; SI-SAFE: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; SI: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
-; SI-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
-
-; VI-SAFE: v_cmp_nlt_f32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
-
-; VI-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; VI: v_cmp_nlt_f32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32(ptr addrspace(1) %out, <4 x float> %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1
@@ -30,22 +24,32 @@ define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32(ptr addrspace(1)
ret void
}
-; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:
-; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}
+; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32_fast:
-; SI-SAFE: v_mov_b32_e32 [[VA:v[0-9]+]], s[[#LOAD + 2]]
+; SI: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
-; GCN-NONAN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]
+; VI: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32_fast(ptr addrspace(1) %out, <4 x float> %reg0) #0 {
+ %r0 = extractelement <4 x float> %reg0, i32 0
+ %r1 = extractelement <4 x float> %reg0, i32 1
+ %r2 = fcmp nnan nsz uge float %r0, %r1
+ %r3 = select nnan nsz i1 %r2, float %r1, float %r0
+ store float %r3, ptr addrspace(1) %out
+ ret void
+}
-; VI-SAFE: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]
+; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:
+; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}
+
+; SI: v_mov_b32_e32 [[VA:v[0-9]+]], s[[#LOAD + 2]]
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, s[[#LOAD + 3]], [[VA]]
+; VI: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]
-; VI-SAFE: v_mov_b32_e32 [[VA:v[0-9]+]], s[[#LOAD + 2]]
-; VI-SAFE: v_cmp_ngt_f32_e32 vcc, s[[#LOAD + 2]], [[VB]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[VB]], [[VA]]
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, s[[#LOAD + 3]], [[VA]]
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, s[[#LOAD + 2]], [[VB]]
+; VI: v_mov_b32_e32 [[VA:v[0-9]+]], s[[#LOAD + 2]]
+; VI: v_cmp_ngt_f32_e32 vcc, s[[#LOAD + 2]], [[VB]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[VB]], [[VA]]
define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(ptr addrspace(1) %out, float %a, float %b) #0 {
%cmp = fcmp ule float %a, %b
%val = select i1 %cmp, float %a, float %b
@@ -53,6 +57,19 @@ define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(ptr addrspace(1) %out, flo
ret void
}
+; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32_fast:
+; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}
+
+; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]
+
+; GCN: v_min_f32_e32 {{v[0-9]+}}, s[[#LOAD + 2]], [[VB]]
+define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_fast(ptr addrspace(1) %out, float %a, float %b) #0 {
+ %cmp = fcmp ule float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
; Nsz also needed
; FIXME: Should separate tests
; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src:
@@ -61,12 +78,10 @@ define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(ptr addrspace(1) %out, flo
; GCN-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#LOAD + 2]], 1.0
; GCN-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#LOAD + 3]], 2.0
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
-
-; VI-SAFE: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
-; VI-SAFE: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
+; VI: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
+; VI: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc
define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src(ptr addrspace(1) %out, float %a, float %b) #0 {
%a.nnan = fadd nnan float %a, 1.0
%b.nnan = fadd nnan float %b, 2.0
@@ -76,16 +91,32 @@ define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src(ptr addrspace(1)
ret void
}
+; Nsz also needed
+; FIXME: Should separate tests
+; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src_fast:
+; GCN: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}
+
+; GCN-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#LOAD + 2]], 1.0
+; GCN-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#LOAD + 3]], 2.0
+
+; GCN: v_min_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
+define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src_fast(ptr addrspace(1) %out, float %a, float %b) #0 {
+ %a.nnan = fadd nnan float %a, 1.0
+ %b.nnan = fadd nnan float %b, 2.0
+ %cmp = fcmp ule float %a.nnan, %b.nnan
+ %val = select nnan nsz i1 %cmp, float %a.nnan, float %b.nnan
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmin_legacy_ule_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; VI-SAFE: v_cmp_ngt_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
-
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; VI: v_cmp_ngt_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
define amdgpu_kernel void @test_fmin_legacy_ule_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
@@ -100,16 +131,33 @@ define amdgpu_kernel void @test_fmin_legacy_ule_f32(ptr addrspace(1) %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32:
+; FUNC-LABEL: {{^}}test_fmin_legacy_ule_f32_fast:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+define amdgpu_kernel void @test_fmin_legacy_ule_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
-; VI-SAFE: v_cmp_le_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+ %cmp = fcmp ule float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+
+; VI: v_cmp_le_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
define amdgpu_kernel void @test_fmin_legacy_ole_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
@@ -124,16 +172,33 @@ define amdgpu_kernel void @test_fmin_legacy_ole_f32(ptr addrspace(1) %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}test_fmin_legacy_olt_f32:
+; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32_fast:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+define amdgpu_kernel void @test_fmin_legacy_ole_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
-; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
+
+ %cmp = fcmp ole float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}test_fmin_legacy_olt_f32:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+; VI: v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
define amdgpu_kernel void @test_fmin_legacy_olt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
@@ -148,16 +213,33 @@ define amdgpu_kernel void @test_fmin_legacy_olt_f32(ptr addrspace(1) %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}test_fmin_legacy_ult_f32:
+; FUNC-LABEL: {{^}}test_fmin_legacy_olt_f32_fast:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+define amdgpu_kernel void @test_fmin_legacy_olt_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+ %cmp = fcmp olt float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}test_fmin_legacy_ult_f32:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+
+; VI: v_cmp_nge_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
define amdgpu_kernel void @test_fmin_legacy_ult_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
@@ -172,16 +254,33 @@ define amdgpu_kernel void @test_fmin_legacy_ult_f32(ptr addrspace(1) %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v1f32:
+; FUNC-LABEL: {{^}}test_fmin_legacy_ult_f32_fast:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+define amdgpu_kernel void @test_fmin_legacy_ult_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
-; VI-SAFE: v_cmp_nge_f32_e32 vcc, [[A]], [[B]]
-; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
+ %a = load volatile float, ptr addrspace(1) %gep.0, align 4
+ %b = load volatile float, ptr addrspace(1) %gep.1, align 4
-; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+ %cmp = fcmp ult float %a, %b
+ %val = select nnan nsz i1 %cmp, float %a, float %b
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v1f32:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
+
+; VI: v_cmp_nge_f32_e32 vcc, [[A]], [[B]]
+; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid
@@ -196,19 +295,35 @@ define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(ptr addrspace(1) %out, ptr
ret void
}
+; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v1f32_fast:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
+
+; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
+define amdgpu_kernel void @test_fmin_legacy_ult_v1f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr <1 x float>, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile <1 x float>, ptr addrspace(1) %gep.0
+ %b = load volatile <1 x float>, ptr addrspace(1) %gep.1
+
+ %cmp = fcmp ult <1 x float> %a, %b
+ %val = select nnan nsz <1 x i1> %cmp, <1 x float> %a, <1 x float> %b
+ store <1 x float> %val, ptr addrspace(1) %out
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32:
; GCN: {{buffer|flat}}_load_dwordx2
; GCN: {{buffer|flat}}_load_dwordx2
-; SI-SAFE: v_min_legacy_f32_e32
-; SI-SAFE: v_min_legacy_f32_e32
-
-; VI-SAFE: v_cmp_nge_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE: v_cmp_nge_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
+; SI: v_min_legacy_f32_e32
+; SI: v_min_legacy_f32_e32
-; GCN-NONAN: v_min_f32_e32
-; GCN-NONAN: v_min_f32_e32
+; VI: v_cmp_nge_f32_e32
+; VI: v_cndmask_b32_e32
+; VI: v_cmp_nge_f32_e32
+; VI: v_cndmask_b32_e32
define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr <2 x float>, ptr addrspace(1) %in, i32 %tid
@@ -223,25 +338,40 @@ define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(ptr addrspace(1) %out, ptr
ret void
}
+; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32_fast:
+; GCN: {{buffer|flat}}_load_dwordx2
+; GCN: {{buffer|flat}}_load_dwordx2
+
+; GCN: v_min_f32_e32
+; GCN: v_min_f32_e32
+define amdgpu_kernel void @test_fmin_legacy_ult_v2f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr <2 x float>, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr <2 x float>, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load volatile <2 x float>, ptr addrspace(1) %gep.0
+ %b = load volatile <2 x float>, ptr addrspace(1) %gep.1
+
+ %cmp = fcmp ult <2 x float> %a, %b
+ %val = select nnan nsz <2 x i1> %cmp, <2 x float> %a, <2 x float> %b
+ store <2 x float> %val, ptr addrspace(1) %out
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32:
-; SI-SAFE: v_min_legacy_f32_e32
-; SI-SAFE: v_min_legacy_f32_e32
-; SI-SAFE: v_min_legacy_f32_e32
-; SI-SAFE-NOT: v_min_
-
-; VI-SAFE: v_cmp_nge_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE: v_cmp_nge_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE: v_cmp_nge_f32_e32
-; VI-SAFE: v_cndmask_b32_e32
+; SI: v_min_legacy_f32_e32
+; SI: v_min_legacy_f32_e32
+; SI: v_min_legacy_f32_e32
+; SI-NOT: v_min_
+
+; VI: v_cmp_nge_f32_e32
+; VI: v_cndmask_b32_e32
+; VI: v_cmp_nge_f32_e32
+; VI: v_cndmask_b32_e32
+; VI: v_cmp_nge_f32_e32
+; VI: v_cndmask_b32_e32
; VI-NOT: v_cmp
; VI-NOT: v_cndmask
-
-; GCN-NONAN: v_min_f32_e32
-; GCN-NONAN: v_min_f32_e32
-; GCN-NONAN: v_min_f32_e32
-; GCN-NONAN-NOT: v_min_
define amdgpu_kernel void @test_fmin_legacy_ult_v3f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid
@@ -256,6 +386,28 @@ define amdgpu_kernel void @test_fmin_legacy_ult_v3f32(ptr addrspace(1) %out, ptr
ret void
}
+; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32_fast:
+; VI-NOT: v_cmp
+; VI-NOT: v_cndmask
+
+; GCN: v_min_f32_e32
+; GCN: v_min_f32_e32
+; GCN: v_min_f32_e32
+; GCN-NOT: v_min_
+define amdgpu_kernel void @test_fmin_legacy_ult_v3f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid
+ %gep.1 = getelementptr <3 x float>, ptr addrspace(1) %gep.0, i32 1
+
+ %a = load <3 x float>, ptr addrspace(1) %gep.0
+ %b = load <3 x float>, ptr addrspace(1) %gep.1
+
+ %cmp = fcmp ult <3 x float> %a, %b
+ %val = select nnan nsz <3 x i1> %cmp, <3 x float> %a, <3 x float> %b
+ store <3 x float> %val, ptr addrspace(1) %out
+ ret void
+}
+
; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32_multi_use:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
diff --git a/llvm/test/CodeGen/NVPTX/bug22322.ll b/llvm/test/CodeGen/NVPTX/bug22322.ll
index 055c512401b4c..71e180b39fcf9 100644
--- a/llvm/test/CodeGen/NVPTX/bug22322.ll
+++ b/llvm/test/CodeGen/NVPTX/bug22322.ll
@@ -20,12 +20,12 @@ _ZL11compute_vecRK6float3jb.exit:
call void @llvm.lifetime.start.p0(i64 4, ptr %ret_vec.sroa.8.i)
%6 = and i32 %4, 15
%7 = icmp eq i32 %6, 0
- %8 = select i1 %7, float 0.000000e+00, float -1.000000e+00
+ %8 = select nnan nsz i1 %7, float 0.000000e+00, float -1.000000e+00
store float %8, ptr %ret_vec.sroa.8.i, align 4
; CHECK: max.f32 %r{{[0-9]+}}, %r{{[0-9]+}}, 0f00000000
%9 = fcmp olt float %8, 0.000000e+00
%ret_vec.sroa.8.i.val = load float, ptr %ret_vec.sroa.8.i, align 4
- %10 = select i1 %9, float 0.000000e+00, float %ret_vec.sroa.8.i.val
+ %10 = select nnan nsz i1 %9, float 0.000000e+00, float %ret_vec.sroa.8.i.val
call void @llvm.lifetime.end.p0(i64 4, ptr %ret_vec.sroa.8.i)
%11 = getelementptr inbounds %class.float3, ptr %dst, i64 %5, i32 0
store float 0.000000e+00, ptr %11, align 4
@@ -51,7 +51,7 @@ declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #2
; Function Attrs: nounwind
declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #2
-attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "no-signed-zeros-fp-math"="true" "use-soft-float"="false" }
+attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/scalar-min-max.ll b/llvm/test/CodeGen/PowerPC/scalar-min-max.ll
index 216d498e85411..5f637e3ecddd3 100644
--- a/llvm/test/CodeGen/PowerPC/scalar-min-max.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-min-max.ll
@@ -1,36 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names --enable-unsafe-fp-math \
-; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \
-; RUN: --enable-no-nans-fp-math \
-; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
-; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names --enable-unsafe-fp-math \
-; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \
-; RUN: --enable-no-nans-fp-math \
-; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
-; RUN: --check-prefix=NO-FAST-P9
+; RUN: --check-prefix=P9
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
-; RUN: --check-prefix=NO-FAST-P8
+; RUN: --check-prefix=P8
define dso_local float @testfmax(float %a, float %b) local_unnamed_addr {
-; CHECK-LABEL: testfmax:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmaxdp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testfmax:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmaxcdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testfmax:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2
-; NO-FAST-P8-NEXT: bgtlr cr0
-; NO-FAST-P8-NEXT: # %bb.1: # %entry
-; NO-FAST-P8-NEXT: fmr f1, f2
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testfmax:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmaxcdp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testfmax:
+; P8: # %bb.0: # %entry
+; P8-NEXT: fcmpu cr0, f1, f2
+; P8-NEXT: bgtlr cr0
+; P8-NEXT: # %bb.1: # %entry
+; P8-NEXT: fmr f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp ogt float %a, %b
%cond = select i1 %cmp, float %a, float %b
@@ -38,23 +25,18 @@ entry:
}
define dso_local double @testdmax(double %a, double %b) local_unnamed_addr {
-; CHECK-LABEL: testdmax:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmaxdp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testdmax:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmaxcdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testdmax:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2
-; NO-FAST-P8-NEXT: bgtlr cr0
-; NO-FAST-P8-NEXT: # %bb.1: # %entry
-; NO-FAST-P8-NEXT: fmr f1, f2
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testdmax:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmaxcdp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testdmax:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xscmpudp cr0, f1, f2
+; P8-NEXT: bgtlr cr0
+; P8-NEXT: # %bb.1: # %entry
+; P8-NEXT: fmr f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp ogt double %a, %b
%cond = select i1 %cmp, double %a, double %b
@@ -62,23 +44,18 @@ entry:
}
define dso_local float @testfmin(float %a, float %b) local_unnamed_addr {
-; CHECK-LABEL: testfmin:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmindp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testfmin:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmincdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testfmin:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2
-; NO-FAST-P8-NEXT: bltlr cr0
-; NO-FAST-P8-NEXT: # %bb.1: # %entry
-; NO-FAST-P8-NEXT: fmr f1, f2
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testfmin:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmincdp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testfmin:
+; P8: # %bb.0: # %entry
+; P8-NEXT: fcmpu cr0, f1, f2
+; P8-NEXT: bltlr cr0
+; P8-NEXT: # %bb.1: # %entry
+; P8-NEXT: fmr f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp olt float %a, %b
%cond = select i1 %cmp, float %a, float %b
@@ -86,23 +63,18 @@ entry:
}
define dso_local double @testdmin(double %a, double %b) local_unnamed_addr {
-; CHECK-LABEL: testdmin:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmindp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testdmin:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmincdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testdmin:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2
-; NO-FAST-P8-NEXT: bltlr cr0
-; NO-FAST-P8-NEXT: # %bb.1: # %entry
-; NO-FAST-P8-NEXT: fmr f1, f2
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testdmin:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmincdp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testdmin:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xscmpudp cr0, f1, f2
+; P8-NEXT: bltlr cr0
+; P8-NEXT: # %bb.1: # %entry
+; P8-NEXT: fmr f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp olt double %a, %b
%cond = select i1 %cmp, double %a, double %b
@@ -110,86 +82,62 @@ entry:
}
define dso_local float @testfmax_fast(float %a, float %b) local_unnamed_addr {
-; CHECK-LABEL: testfmax_fast:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmaxdp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testfmax_fast:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmaxcdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testfmax_fast:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xssubsp f0, f2, f1
-; NO-FAST-P8-NEXT: fsel f1, f0, f2, f1
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testfmax_fast:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmaxdp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testfmax_fast:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xsmaxdp f1, f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp nnan ninf ogt float %a, %b
- %cond = select i1 %cmp, float %a, float %b
+ %cond = select nnan nsz i1 %cmp, float %a, float %b
ret float %cond
}
define dso_local double @testdmax_fast(double %a, double %b) local_unnamed_addr {
-; CHECK-LABEL: testdmax_fast:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmaxdp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testdmax_fast:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmaxcdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testdmax_fast:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xssubdp f0, f2, f1
-; NO-FAST-P8-NEXT: fsel f1, f0, f2, f1
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testdmax_fast:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmaxdp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testdmax_fast:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xsmaxdp f1, f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp nnan ninf ogt double %a, %b
- %cond = select i1 %cmp, double %a, double %b
+ %cond = select nnan nsz i1 %cmp, double %a, double %b
ret double %cond
}
define dso_local float @testfmin_fast(float %a, float %b) local_unnamed_addr {
-; CHECK-LABEL: testfmin_fast:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmindp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testfmin_fast:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmincdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testfmin_fast:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xssubsp f0, f1, f2
-; NO-FAST-P8-NEXT: fsel f1, f0, f2, f1
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testfmin_fast:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmindp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testfmin_fast:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xsmindp f1, f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp nnan ninf olt float %a, %b
- %cond = select i1 %cmp, float %a, float %b
+ %cond = select nnan nsz i1 %cmp, float %a, float %b
ret float %cond
}
define dso_local double @testdmin_fast(double %a, double %b) local_unnamed_addr {
-; CHECK-LABEL: testdmin_fast:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsmindp f1, f1, f2
-; CHECK-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testdmin_fast:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xsmincdp f1, f1, f2
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testdmin_fast:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xssubdp f0, f1, f2
-; NO-FAST-P8-NEXT: fsel f1, f0, f2, f1
-; NO-FAST-P8-NEXT: blr
+; P9-LABEL: testdmin_fast:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xsmindp f1, f1, f2
+; P9-NEXT: blr
+;
+; P8-LABEL: testdmin_fast:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xsmindp f1, f1, f2
+; P8-NEXT: blr
entry:
%cmp = fcmp nnan ninf olt double %a, %b
- %cond = select i1 %cmp, double %a, double %b
+ %cond = select nnan nsz i1 %cmp, double %a, double %b
ret double %cond
}
diff --git a/llvm/test/CodeGen/VE/Scalar/max.ll b/llvm/test/CodeGen/VE/Scalar/max.ll
index 51da557c6c49f..7950842670afb 100644
--- a/llvm/test/CodeGen/VE/Scalar/max.ll
+++ b/llvm/test/CodeGen/VE/Scalar/max.ll
@@ -1,7 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
-; RUN: llc < %s -mtriple=ve-unknown-unknown -enable-no-signed-zeros-fp-math \
-; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=OPT
define double @maxf64(double, double) {
; CHECK-LABEL: maxf64:
@@ -10,16 +8,21 @@ define double @maxf64(double, double) {
; CHECK-NEXT: cmov.d.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxf64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @maxf64_fast(double, double) {
+; CHECK-LABEL: maxf64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ogt double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
define double @max2f64(double, double) {
; CHECK-LABEL: max2f64:
; CHECK: # %bb.0:
@@ -27,16 +30,21 @@ define double @max2f64(double, double) {
; CHECK-NEXT: cmov.d.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2f64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @max2f64_fast(double, double) {
+; CHECK-LABEL: max2f64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp oge double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
; VE has no max for unordered comparison
define double @maxuf64(double, double) {
; CHECK-LABEL: maxuf64:
@@ -45,16 +53,21 @@ define double @maxuf64(double, double) {
; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxuf64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @maxuf64_fast(double, double) {
+; CHECK-LABEL: maxuf64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ugt double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
; VE has no max for unordered comparison
define double @max2uf64(double, double) {
; CHECK-LABEL: max2uf64:
@@ -63,16 +76,21 @@ define double @max2uf64(double, double) {
; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2uf64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @max2uf64_fast(double, double) {
+; CHECK-LABEL: max2uf64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp uge double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
define float @maxf32(float, float) {
; CHECK-LABEL: maxf32:
; CHECK: # %bb.0:
@@ -80,16 +98,21 @@ define float @maxf32(float, float) {
; CHECK-NEXT: cmov.s.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxf32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @maxf32_fast(float, float) {
+; CHECK-LABEL: maxf32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ogt float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define float @max2f32(float, float) {
; CHECK-LABEL: max2f32:
; CHECK: # %bb.0:
@@ -97,16 +120,21 @@ define float @max2f32(float, float) {
; CHECK-NEXT: cmov.s.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2f32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @max2f32_fast(float, float) {
+; CHECK-LABEL: max2f32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp oge float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define float @maxuf32(float, float) {
; CHECK-LABEL: maxuf32:
; CHECK: # %bb.0:
@@ -114,16 +142,21 @@ define float @maxuf32(float, float) {
; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxuf32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @maxuf32_fast(float, float) {
+; CHECK-LABEL: maxuf32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ugt float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define float @max2uf32(float, float) {
; CHECK-LABEL: max2uf32:
; CHECK: # %bb.0:
@@ -131,26 +164,26 @@ define float @max2uf32(float, float) {
; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2uf32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmax.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @max2uf32_fast(float, float) {
+; CHECK-LABEL: max2uf32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmax.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp uge float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define i64 @maxi64(i64, i64) {
; CHECK-LABEL: maxi64:
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxi64:
-; OPT: # %bb.0:
-; OPT-NEXT: maxs.l %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -161,11 +194,6 @@ define i64 @max2i64(i64, i64) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2i64:
-; OPT: # %bb.0:
-; OPT-NEXT: maxs.l %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -178,13 +206,6 @@ define i64 @maxu64(i64, i64) {
; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxu64:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.l %s2, %s0, %s1
-; OPT-NEXT: cmov.l.gt %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -197,13 +218,6 @@ define i64 @max2u64(i64, i64) {
; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2u64:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.l %s2, %s0, %s1
-; OPT-NEXT: cmov.l.ge %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -214,11 +228,6 @@ define i32 @maxi32(i32, i32) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxi32:
-; OPT: # %bb.0:
-; OPT-NEXT: maxs.w.sx %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -229,11 +238,6 @@ define i32 @max2i32(i32, i32) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2i32:
-; OPT: # %bb.0:
-; OPT-NEXT: maxs.w.sx %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -246,13 +250,6 @@ define i32 @maxu32(i32, i32) {
; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxu32:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.w %s2, %s0, %s1
-; OPT-NEXT: cmov.w.gt %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -265,13 +262,6 @@ define i32 @max2u32(i32, i32) {
; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: max2u32:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.w %s2, %s0, %s1
-; OPT-NEXT: cmov.w.ge %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -283,12 +273,6 @@ define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: maxi1:
-; OPT: # %bb.0:
-; OPT-NEXT: or %s0, %s0, %s1
-; OPT-NEXT: and %s0, 1, %s0
-; OPT-NEXT: b.l.t (, %s10)
%3 = xor i1 %1, true
%4 = and i1 %3, %0
%5 = select i1 %4, i1 %0, i1 %1
diff --git a/llvm/test/CodeGen/VE/Scalar/min.ll b/llvm/test/CodeGen/VE/Scalar/min.ll
index e8f4939f9149e..36a2e06a2c9d4 100644
--- a/llvm/test/CodeGen/VE/Scalar/min.ll
+++ b/llvm/test/CodeGen/VE/Scalar/min.ll
@@ -1,7 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
-; RUN: llc < %s -mtriple=ve-unknown-unknown -enable-no-signed-zeros-fp-math \
-; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=OPT
define double @minf64(double, double) {
; CHECK-LABEL: minf64:
@@ -10,16 +8,21 @@ define double @minf64(double, double) {
; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: minf64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @minf64_fast(double, double) {
+; CHECK-LABEL: minf64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp olt double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
define double @min2f64(double, double) {
; CHECK-LABEL: min2f64:
; CHECK: # %bb.0:
@@ -27,16 +30,21 @@ define double @min2f64(double, double) {
; CHECK-NEXT: cmov.d.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2f64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @min2f64_fast(double, double) {
+; CHECK-LABEL: min2f64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ole double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
define double @minuf64(double, double) {
; CHECK-LABEL: minuf64:
; CHECK: # %bb.0:
@@ -44,16 +52,21 @@ define double @minuf64(double, double) {
; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: minuf64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @minuf64_fast(double, double) {
+; CHECK-LABEL: minuf64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ult double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
define double @min2uf64(double, double) {
; CHECK-LABEL: min2uf64:
; CHECK: # %bb.0:
@@ -61,16 +74,21 @@ define double @min2uf64(double, double) {
; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2uf64:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.d %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
}
+define double @min2uf64_fast(double, double) {
+; CHECK-LABEL: min2uf64_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.d %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ule double %0, %1
+ %4 = select nnan nsz i1 %3, double %0, double %1
+ ret double %4
+}
+
define float @minf32(float, float) {
; CHECK-LABEL: minf32:
; CHECK: # %bb.0:
@@ -78,16 +96,21 @@ define float @minf32(float, float) {
; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: minf32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @minf32_fast(float, float) {
+; CHECK-LABEL: minf32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp olt float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define float @min2f32(float, float) {
; CHECK-LABEL: min2f32:
; CHECK: # %bb.0:
@@ -95,16 +118,21 @@ define float @min2f32(float, float) {
; CHECK-NEXT: cmov.s.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2f32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @min2f32_fast(float, float) {
+; CHECK-LABEL: min2f32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ole float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define float @minuf32(float, float) {
; CHECK-LABEL: minuf32:
; CHECK: # %bb.0:
@@ -112,16 +140,21 @@ define float @minuf32(float, float) {
; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: minuf32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @minuf32_fast(float, float) {
+; CHECK-LABEL: minuf32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ult float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define float @min2uf32(float, float) {
; CHECK-LABEL: min2uf32:
; CHECK: # %bb.0:
@@ -129,26 +162,26 @@ define float @min2uf32(float, float) {
; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2uf32:
-; OPT: # %bb.0:
-; OPT-NEXT: fmin.s %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
}
+define float @min2uf32_fast(float, float) {
+; CHECK-LABEL: min2uf32_fast:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmin.s %s0, %s0, %s1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = fcmp ule float %0, %1
+ %4 = select nnan nsz i1 %3, float %0, float %1
+ ret float %4
+}
+
define i64 @mini64(i64, i64) {
; CHECK-LABEL: mini64:
; CHECK: # %bb.0:
; CHECK-NEXT: mins.l %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: mini64:
-; OPT: # %bb.0:
-; OPT-NEXT: mins.l %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -159,11 +192,6 @@ define i64 @min2i64(i64, i64) {
; CHECK: # %bb.0:
; CHECK-NEXT: mins.l %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2i64:
-; OPT: # %bb.0:
-; OPT-NEXT: mins.l %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -176,13 +204,6 @@ define i64 @minu64(i64, i64) {
; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: minu64:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.l %s2, %s0, %s1
-; OPT-NEXT: cmov.l.lt %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -195,13 +216,6 @@ define i64 @min2u64(i64, i64) {
; CHECK-NEXT: cmov.l.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2u64:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.l %s2, %s0, %s1
-; OPT-NEXT: cmov.l.le %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@@ -212,11 +226,6 @@ define i32 @mini32(i32, i32) {
; CHECK: # %bb.0:
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: mini32:
-; OPT: # %bb.0:
-; OPT-NEXT: mins.w.sx %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -227,11 +236,6 @@ define i32 @min2i32(i32, i32) {
; CHECK: # %bb.0:
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2i32:
-; OPT: # %bb.0:
-; OPT-NEXT: mins.w.sx %s0, %s0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -244,13 +248,6 @@ define i32 @minu32(i32, i32) {
; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: minu32:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.w %s2, %s0, %s1
-; OPT-NEXT: cmov.w.lt %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -263,13 +260,6 @@ define i32 @min2u32(i32, i32) {
; CHECK-NEXT: cmov.w.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: min2u32:
-; OPT: # %bb.0:
-; OPT-NEXT: cmpu.w %s2, %s0, %s1
-; OPT-NEXT: cmov.w.le %s1, %s0, %s2
-; OPT-NEXT: or %s0, 0, %s1
-; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@@ -283,14 +273,6 @@ define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {
; CHECK-NEXT: cmov.w.ne %s0, %s1, %s2
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
-;
-; OPT-LABEL: mini1:
-; OPT: # %bb.0:
-; OPT-NEXT: and %s2, 1, %s0
-; OPT-NEXT: and %s0, %s1, %s0
-; OPT-NEXT: cmov.w.ne %s0, %s1, %s2
-; OPT-NEXT: adds.w.zx %s0, %s0, (0)1
-; OPT-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, true
%4 = and i1 %3, %1
%5 = select i1 %4, i1 %0, i1 %1
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