[llvm] 1f82553 - [SLP]Fix mixing xor instructions in the same opcode analysis

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2025-09-29T11:14:06-07:00
New Revision: 1f82553e385f449efee92da3dca43facb4a1ee66

URL: https://github.com/llvm/llvm-project/commit/1f82553e385f449efee92da3dca43facb4a1ee66
DIFF: https://github.com/llvm/llvm-project/commit/1f82553e385f449efee92da3dca43facb4a1ee66.diff

LOG: [SLP]Fix mixing xor instructions in the same opcode analysis

Xor with 0 operand should not be compatible with multiplications-based
instructions, only with or/xor/add/sub.

Fixes #161140

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 065622efc7ecc..c547662c3a77e 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -1100,7 +1100,9 @@ class BinOpSameOpcodeHelper {
       // constant + x cannot be -constant - x
       // instead, it should be x - -constant
       if (Pos == 1 ||
-          (FromOpcode == Instruction::Add && ToOpcode == Instruction::Sub))
+          ((FromOpcode == Instruction::Add || FromOpcode == Instruction::Or ||
+            FromOpcode == Instruction::Xor) &&
+           ToOpcode == Instruction::Sub))
         return SmallVector<Value *>({LHS, RHS});
       return SmallVector<Value *>({RHS, LHS});
     }
@@ -1188,6 +1190,10 @@ class BinOpSameOpcodeHelper {
         if (CIValue.isAllOnes())
           InterchangeableMask = CanBeAll;
         break;
+      case Instruction::Xor:
+        if (CIValue.isZero())
+          InterchangeableMask = XorBIT | OrBIT | AndBIT | SubBIT | AddBIT;
+        break;
       default:
         if (CIValue.isZero())
           InterchangeableMask = CanBeAll;

diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll b/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
index 7664fda8c5a3c..9cdcdf1b5d5ca 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
@@ -6,7 +6,7 @@ define i1 @foo(i1 %v) {            ; assume %v is 1
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <2 x i1> poison, i1 [[V]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i1> [[TMP0]], <2 x i1> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = mul <2 x i1> <i1 false, i1 true>, [[TMP1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = xor <2 x i1> zeroinitializer, [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i1 [[TMP3]], [[TMP4]]