[llvm] 0457644 - [SLP][NFC]Add a test with the incorrect combination of Xor/Mul vector instructions, NFC

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2025-09-29T10:37:39-07:00
New Revision: 0457644dfb0465cde08d25f4bd704b4b8e7a355c

URL: https://github.com/llvm/llvm-project/commit/0457644dfb0465cde08d25f4bd704b4b8e7a355c
DIFF: https://github.com/llvm/llvm-project/commit/0457644dfb0465cde08d25f4bd704b4b8e7a355c.diff

LOG: [SLP][NFC]Add a test with the incorrect combination of Xor/Mul vector instructions, NFC

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll b/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
new file mode 100644
index 0000000000000..7664fda8c5a3c
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s -slp-threshold=-100 | FileCheck %s
+define i1 @foo(i1 %v) {            ; assume %v is 1
+; CHECK-LABEL: define i1 @foo(
+; CHECK-SAME: i1 [[V:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <2 x i1> poison, i1 [[V]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i1> [[TMP0]], <2 x i1> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = mul <2 x i1> <i1 false, i1 true>, [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
+; CHECK-NEXT:    [[SUB:%.*]] = sub i1 [[TMP3]], [[TMP4]]
+; CHECK-NEXT:    ret i1 [[SUB]]
+;
+entry:
+  %not = xor i1 %v, 1              ; 0
+  %not1 = xor i1 %not, 1           ; 1
+  %mul = mul i1 %v, 1              ; 1
+  %sub = sub i1 %not1, %mul        ; 0
+  ret i1 %sub                      ; 0
+}