[llvm] Fold SVE mul and mul_u to neg during isel (PR #160828)

[via llvm-commits]

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@@ -723,6 +723,19 @@ class SVE2p1_Cvt_VG2_Pat<string name, SDPatternOperator intrinsic, ValueType out
     : Pat<(out_vt (intrinsic in_vt:$Zn1, in_vt:$Zn2)),
                   (!cast<Instruction>(name) (REG_SEQUENCE ZPR2Mul2, in_vt:$Zn1, zsub0, in_vt:$Zn2, zsub1))>;
 
+class SVE_2_Op_Neg_One_Passthru_Pat<ValueType vt, SDPatternOperator op, ValueType pt,
+                             Instruction inst, ValueType immT>
+: Pat<(vt (op pt:$Op1, vt:$Op2, (vt (splat_vector (immT -1))))),
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Lukacma wrote:

I think that similarly to AArch64bic we need to extend this to work for both 32 and 64 bit splats. Or is there a reason why you are enabling it only for one or the other ?

https://github.com/llvm/llvm-project/pull/160828