[llvm] [AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned (PR #160547)

[Janek van Oirschot via llvm-commits]

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@@ -93,12 +93,3 @@ body: |
   bb.0:
     $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
 ...
-
-# GCN-LABEL: name: v_mov_b64_misalign
-# GCN: $vgpr5 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr5_vgpr6
-# GCN: $vgpr6 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr5_vgpr6
-name: v_mov_b64_misalign
-body: |
-  bb.0:
-    $vgpr5_vgpr6 = V_MOV_B64_PSEUDO 0, implicit $exec
-...
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JanekvO wrote:

Because `V_MOV_B64_PSEUDO` is regclass constrained, even the MIRParser will error on a misaligned register pair. Therefore, removing this test.

https://github.com/llvm/llvm-project/pull/160547