[llvm] ce70773 - Fix some typos in machine verifier comments and trace output (#160049)

[via llvm-commits]

Author: DST
Date: 2025-09-29T10:23:09Z
New Revision: ce70773cff2ab6b5d9b8d7a97ee62c75762a51d2

URL: https://github.com/llvm/llvm-project/commit/ce70773cff2ab6b5d9b8d7a97ee62c75762a51d2
DIFF: https://github.com/llvm/llvm-project/commit/ce70773cff2ab6b5d9b8d7a97ee62c75762a51d2.diff

LOG: Fix some typos in machine verifier comments and trace output (#160049)

Stumbled across a typo in the `MachineVerifier` file and since I had it
open, I changed some other comments.

Not important but why not leave it a bit cleaner :slightly_smiling_face:

---------

Signed-off-by: Daniel Stadelmann <dasta_7 at hotmail.com>

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineVerifier.cpp
    llvm/test/MachineVerifier/test_g_build_vector.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index e911ce8a75828..115485509c4a5 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1549,7 +1549,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
       report("G_BUILD_VECTOR result element type must match source type", MI);
 
     if (DstTy.getNumElements() != MI->getNumOperands() - 1)
-      report("G_BUILD_VECTOR must have an operand for each elemement", MI);
+      report("G_BUILD_VECTOR must have an operand for each element", MI);
 
     for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
       if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
@@ -2398,11 +2398,11 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
 
     // The next two checks allow COPY between physical and virtual registers,
     // when the virtual register has a scalable size and the physical register
-    // has a fixed size. These checks allow COPY between *potentialy* mismatched
-    // sizes. However, once RegisterBankSelection occurs, MachineVerifier should
-    // be able to resolve a fixed size for the scalable vector, and at that
-    // point this function will know for sure whether the sizes are mismatched
-    // and correctly report a size mismatch.
+    // has a fixed size. These checks allow COPY between *potentially*
+    // mismatched sizes. However, once RegisterBankSelection occurs,
+    // MachineVerifier should be able to resolve a fixed size for the scalable
+    // vector, and at that point this function will know for sure whether the
+    // sizes are mismatched and correctly report a size mismatch.
     if (SrcReg.isPhysical() && DstReg.isVirtual() && DstSize.isScalable() &&
         !SrcSize.isScalable())
       break;
@@ -3213,13 +3213,13 @@ struct VRegFilter {
 
 private:
   static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
-  // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
-  // are tracked by Dense. The only purpose of the threashold and the Dense set
+  // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyond
+  // are tracked by Dense. The only purpose of the threshold and the Dense set
   // is to have a reasonably growing memory usage in pathological cases (large
   // number of very sparse VRegFilter instances live at the same time). In
   // practice even in the worst-by-execution time cases having all elements
   // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
-  // space efficient than if tracked by Dense. The threashold is set to keep the
+  // space efficient than if tracked by Dense. The threshold is set to keep the
   // worst-case memory usage within 2x of figures determined empirically for
   // "all Dense" scenario in such worst-by-execution-time cases.
   BitVector Sparse;
@@ -3459,7 +3459,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
 
   // Check live-in list of each MBB. If a register is live into MBB, check
   // that the register is in regsLiveOut of each predecessor block. Since
-  // this must come from a definition in the predecesssor or its live-in
+  // this must come from a definition in the predecessor or its live-in
   // list, this will catch a live-through case where the predecessor does not
   // have the register in its live-in list.  This currently only checks
   // registers that have no aliases, are not allocatable and are not

diff  --git a/llvm/test/MachineVerifier/test_g_build_vector.mir b/llvm/test/MachineVerifier/test_g_build_vector.mir
index 50b98017a49a7..9857306737108 100644
--- a/llvm/test/MachineVerifier/test_g_build_vector.mir
+++ b/llvm/test/MachineVerifier/test_g_build_vector.mir
@@ -16,17 +16,17 @@ body:             |
     ; CHECK: Bad machine code: G_BUILD_VECTOR must produce a vector from scalar operands
     %3:_(<2 x s32>) = G_BUILD_VECTOR %2
 
-    ; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each elemement
+    ; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each element
     %4:_(<2 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
 
     ; CHECK: Bad machine code: G_BUILD_VECTOR result element type must match source type
-    ; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each elemement
+    ; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each element
     %5:_(<4 x s16>) = G_BUILD_VECTOR %0, %0
 
     %6:_(s16) = IMPLICIT_DEF
 
     ; CHECK: Bad machine code: G_BUILD_VECTOR result element type must match source type
-    ; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each elemement
+    ; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each element
     %7:_(<2 x s32>) = G_BUILD_VECTOR %6, %6, %6, %6
 
     %8:_(p0) = IMPLICIT_DEF