[llvm] [AMDGPU] Sink uniform buffer address offsets into soffset (PR #160939)

[Prasoon Mishra via llvm-commits]

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@@ -341,8 +338,23 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
 
     switch (N->getOpcode()) {
     case ISD::BUILD_VECTOR:
-      // TODO: Match load d16 from shl (extload:i16), 16
-      MadeChange |= matchLoadD16FromBuildVector(N);
+      // D16 optimization requires subtarget support
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PrasoonMishra wrote:

@arsenm Thank you for the architectural guidance. I wasn't aware of the RMW property distinction that justifies the d16 optimization in the PreprocessISelDAG. 
As suggested an IR pass after uniformity analysis will be better. This would also enable the s_buffer_load promotion mentioned by @krzysz00. I'll rework this as an IR transformation.

https://github.com/llvm/llvm-project/pull/160939