[llvm] [SPARC] Prevent generic opcodes from being inserted into delay slots (PR #161111)

[via llvm-commits]

https://github.com/koachan created https://github.com/llvm/llvm-project/pull/161111

Do not move instructions with generic opcodes like `FAKE_USE`/`@llvm.fake.use` into delay slots, as they are not real machine instructions.

This should fix crashes when compiling with, for example, `clang -Og`.

>From ab7b98f418b63999e05eb657666514e477fd55ac Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Mon, 29 Sep 2025 08:45:17 +0700
Subject: [PATCH] [SPARC] Prevent generic opcodes from being inserted into
 delay slots

Do not move instructions with generic opcodes like `FAKE_USE`/`@llvm.fake.use`
into delay slots, as they are not real machine instructions.

This should fix crashes when running `clang -Og`.
---
 llvm/lib/Target/Sparc/DelaySlotFiller.cpp     |  4 +--
 .../CodeGen/SPARC/2011-01-19-DelaySlot.ll     | 26 +++++++++++++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
index 6c19049a001cf..73d03fc271100 100644
--- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -206,8 +206,8 @@ Filler::findDelayInstr(MachineBasicBlock &MBB,
     if (!done)
       --I;
 
-    // skip debug instruction
-    if (I->isDebugInstr())
+    // Skip debug and generic instructions.
+    if (I->isDebugInstr() || (I->getOpcode() <= TargetOpcode::GENERIC_OP_END))
       continue;
 
     if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
diff --git a/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 9ccd4f1c0ac9a..d4b21b248d60d 100644
--- a/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -184,4 +184,30 @@ entry:
   ret i32 %2
 }
 
+define i32 @test_generic_inst(i32 %a) #0 {
+;CHECK-LABEL: test_generic_inst:
+;CHECK: ! fake_use: {{.*}}
+;CHECK: bne {{.*}}
+;CHECK-NEXT: nop
+
+%2 = call i32 @bar(i32 %a)
+  %3 = and i32 %2, 1
+  %4 = icmp eq i32 %3, 0
+  ; This shouldn't get reordered into a delay slot
+  call void (...) @llvm.fake.use(i32 %a)
+  br i1 %4, label %5, label %7
+5:
+  %6 = call i32 @bar(i32 %2)
+  br label %9
+
+7:
+  %8 = add nsw i32 %2, 1
+  br label %9
+
+9:
+  %10 = phi i32 [ %6, %5 ], [ %8, %7 ]
+  ret i32 %10
+}
+
+declare void @llvm.fake.use(...)
 attributes #0 = { nounwind "disable-tail-calls"="true" }