[llvm] [ARM] Add mayRaiseFPException to appropriate instructions and mark all instructions that read/write fpscr rounding bits as doing so (PR #160698)

[David Green via llvm-commits]

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@@ -338,7 +338,7 @@ def : MnemonicAlias<"vstm", "vstmia">;
 
 def VLLDM : AXSI4FR<"vlldm${p}\t$Rn, $regs", 0, 1>,
             Requires<[HasV8MMainline, Has8MSecExt]> {
-    let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15];
+    let Defs = [VPR, FPSCR, FPSCR_NZCV, FPSCR_RM, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15];
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davemgreen wrote:

Do these need to be added? I was hoping it would be covered by FPSCR.

https://github.com/llvm/llvm-project/pull/160698