[llvm] [InstCombine] Transform `vector.reduce.add (splat %0, 4)` into `shl i32 %0, 2` (PR #161020)

[Gábor Spaits via llvm-commits]

spaits wrote:

Thank you very much for your review @nikic . I am really happy that you have suggested to optimize the non power of two cases. It was fun implementig those too. :)

- I am now using `getSplatValue` instead of my custom match.
- I am properly constructing `APInt`s now.
- Addeds tests for `i64` types so now there aren't only `i32` tests.

I am also open to any further potential improvement idea for this patch.

https://github.com/llvm/llvm-project/pull/161020