[llvm] [PowerPC] Implement Elliptic Curve Cryptography (ECC) Instructions (PR #158362)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 26 08:12:03 PDT 2025
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/158362
>From 8b474b000fa768b54ce809d6888d6da1cd2915e8 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 23 Sep 2025 10:53:45 -0500
Subject: [PATCH 1/3] [PowerPC] Implement Elliptic Curve Cryptography (ECC)
Instructions
New instructions added:
* xxmulmul
* xxmulmulhiadd
* xxmulmulloadd
* xxssumudm
* xxssumudmc
* xxssumudmcext
* xsaddadduqm
* xsaddaddsuqm
* xsaddsubuqm
* xsaddsubsuqm
* xsmerge2t1uqm
* xsmerge2t2uqm
* xsmerge2t3uqm
* xsmerge3t1uqm
* xsrebase2t1uqm
* xsrebase2t2uqm
* xsrebase2t3uqm
* xsrebase2t4uqm
* xsrebase3t1uqm
* xsrebase3t2uqm
* xsrebase3t3uqm
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 167 ++++++++++++++++++
.../PowerPC/ppc-encoding-ISAFuture.txt | 57 ++++++
.../PowerPC/ppc64le-encoding-ISAFuture.txt | 57 ++++++
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 78 ++++++++
4 files changed, 359 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 9acc3ca7ed788..87ace139bfeb0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -202,6 +202,109 @@ class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = XT{5};
}
+class XX3Form_XTAB6_S<bits<5> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<59, OOL, IOL, asmstr, NoItinerary> {
+ bits<6> XT;
+ bits<6> XA;
+ bits<6> XB;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{24...28} = xo;
+ let Inst{29} = XA{5};
+ let Inst{30} = XB{5};
+ let Inst{31} = XT{5};
+}
+
+class XX3Form_XTAB6_S3<bits<5> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {
+
+ bits<3> S;
+ let Inst{21...23} = S;
+}
+
+class XX3Form_XTAB6_3S1<bits<5> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {
+
+ bits<1> S0;
+ bits<1> S1;
+ bits<1> S2;
+
+ let Inst{21} = S0;
+ let Inst{22} = S1;
+ let Inst{23} = S2;
+}
+
+class XX3Form_XTAB6_2S1<bits<5> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {
+
+ bits<1> S1;
+ bits<1> S2;
+
+ let Inst{21} = 0;
+ let Inst{22} = S1;
+ let Inst{23} = S2;
+}
+
+class XX3Form_XTAB6_P<bits<7> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<59, OOL, IOL, asmstr, NoItinerary> {
+
+ bits<6> XT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<1> P;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21} = P;
+ let Inst{22...28} = xo;
+ let Inst{29} = XA{5};
+ let Inst{30} = XB{5};
+ let Inst{31} = XT{5};
+}
+
+class 8RR_XX4Form_XTABC6_P<bits<6> opcode, bits<1> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ bits<6> XT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<6> XC;
+ bits<1> P;
+
+ let Pattern = pattern;
+
+ // The prefix.
+ let Inst{6...7} = 1;
+ let Inst{8...11} = 0;
+ let Inst{12...13} = 0;
+ let Inst{14...31} = 0;
+
+ // The instruction.
+ let Inst{38...42} = XT{4...0};
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...57} = XC{4...0};
+ let Inst{58} = xo;
+ let Inst{59} = P;
+ let Inst{60} = XC{5};
+ let Inst{61} = XA{5};
+ let Inst{62} = XB{5};
+ let Inst{63} = XT{5};
+}
+
+
//-------------------------- Instruction definitions -------------------------//
// Predicate combinations available:
// [IsISAFuture]
@@ -314,6 +417,70 @@ let Predicates = [HasVSX, IsISAFuture] in {
"xvmulhuw $XT, $XA, $XB", []>;
def XVMULHUH: XX3Form_XTAB6<60, 122, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmulhuh $XT, $XA, $XB", []>;
+
+ // Elliptic Curve Cryptography Acceleration Instructions.
+ def XXMULMUL
+ : XX3Form_XTAB6_S3<1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u3imm:$S),
+ "xxmulmul $XT, $XA, $XB, $S", []>;
+ def XXMULMULHIADD
+ : XX3Form_XTAB6_3S1<9, (outs vsrc:$XT),
+ (ins vsrc:$XA, vsrc:$XB, u1imm:$S0, u1imm:$S1,
+ u1imm:$S2),
+ "xxmulmulhiadd $XT, $XA, $XB, $S0, $S1, $S2", []>;
+ def XXMULMULLOADD
+ : XX3Form_XTAB6_2S1<17, (outs vsrc:$XT),
+ (ins vsrc:$XA, vsrc:$XB, u1imm:$S1, u1imm:$S2),
+ "xxmulmulloadd $XT, $XA, $XB, $S1, $S2", []>;
+ def XXSSUMUDM
+ : XX3Form_XTAB6_P<25, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),
+ "xxssumudm $XT, $XA, $XB, $P", []>;
+ def XXSSUMUDMC
+ : XX3Form_XTAB6_P<57, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),
+ "xxssumudmc $XT, $XA, $XB, $P", []>;
+ def XXSSUMUDMCEXT
+ : 8RR_XX4Form_XTABC6_P<34, 1, (outs vsrc:$XT),
+ (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u1imm:$P),
+ "xxssumudmcext $XT, $XA, $XB, $XC, $P",
+ IIC_VecGeneral, []>;
+ def XSADDADDUQM
+ : XX3Form_XTAB6<59, 96, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsaddadduqm $XT, $XA, $XB", []>;
+ def XSADDADDSUQM
+ : XX3Form_XTAB6<59, 104, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsaddaddsuqm $XT, $XA, $XB", []>;
+ def XSMERGE2T1UQM
+ : XX3Form_XTAB6<59, 232, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsmerge2t1uqm $XT, $XA, $XB", []>;
+ def XSMERGE2T2UQM
+ : XX3Form_XTAB6<59, 240, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsmerge2t2uqm $XT, $XA, $XB", []>;
+ def XSMERGE2T3UQM
+ : XX3Form_XTAB6<59, 89, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsmerge2t3uqm $XT, $XA, $XB", []>;
+ def XSMERGE3T1UQM
+ : XX3Form_XTAB6<59, 121, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsmerge3t1uqm $XT, $XA, $XB", []>;
+ def XSREBASE2T1UQM
+ : XX3Form_XTAB6<59, 145, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase2t1uqm $XT, $XA, $XB", []>;
+ def XSREBASE2T2UQM
+ : XX3Form_XTAB6<59, 177, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase2t2uqm $XT, $XA, $XB", []>;
+ def XSREBASE2T3UQM
+ : XX3Form_XTAB6<59, 209, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase2t3uqm $XT, $XA, $XB", []>;
+ def XSREBASE2T4UQM
+ : XX3Form_XTAB6<59, 217, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase2t4uqm $XT, $XA, $XB", []>;
+ def XSREBASE3T1UQM
+ : XX3Form_XTAB6<59, 241, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase3t1uqm $XT, $XA, $XB", []>;
+ def XSREBASE3T2UQM
+ : XX3Form_XTAB6<59, 249, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase3t2uqm $XT, $XA, $XB", []>;
+ def XSREBASE3T3UQM
+ : XX3Form_XTAB6<59, 195, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xsrebase3t3uqm $XT, $XA, $XB", []>;
}
//---------------------------- Anonymous Patterns ----------------------------//
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index a34e7f54c2234..64e73e494d57d 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -273,3 +273,60 @@
#CHECK: xvmulhuh 4, 5, 7
0xf0,0x85,0x3b,0xd0
+
+#CHECK: xxmulmul 8, 3, 4, 2
+0xed,0x03,0x22,0x08
+
+#CHECK: xxmulmulhiadd 8, 3, 4, 1, 0, 1
+0xed,0x03,0x25,0x48
+
+#CHECK: xxmulmulloadd 8, 3, 4, 1, 0
+0xed,0x03,0x22,0x88
+
+#CHECK: xxssumudm 8, 3, 4, 1
+0xed,0x03,0x24,0xc8
+
+#CHECK: xxssumudmc 8, 3, 4, 1
+0xed,0x03,0x25,0xc8
+
+#CHECK: xxssumudmcext 8, 3, 4, 6, 0
+0x05,0x00,0x00,0x00,0x89,0x03,0x21,0xa0
+
+#CHECK: xsaddadduqm 4, 5, 7
+0xec,0x85,0x3b,0x00
+
+#CHECK: xsaddaddsuqm 4, 5, 7
+0xec,0x85,0x3b,0x40
+
+#CHECK: xsrebase2t1uqm 4, 5, 7
+0xec,0x85,0x3c,0x88
+
+#CHECK: xsrebase2t2uqm 4, 5, 7
+0xec,0x85,0x3d,0x88
+
+#CHECK: xsrebase2t3uqm 4, 5, 7
+0xec,0x85,0x3e,0x88
+
+#CHECK: xsrebase2t4uqm 4, 5, 7
+0xec,0x85,0x3e,0xc8
+
+#CHECK: xsrebase3t1uqm 4, 5, 7
+0xec,0x85,0x3f,0x88
+
+#CHECK: xsrebase3t2uqm 4, 5, 7
+0xec,0x85,0x3f,0xc8
+
+#CHECK: xsrebase3t3uqm 4, 5, 7
+0xec,0x85,0x3e,0x18
+
+#CHECK: xsmerge2t1uqm 4, 5, 7
+0xec,0x85,0x3f,0x40
+
+#CHECK: xsmerge2t2uqm 4, 5, 7
+0xec,0x85,0x3f,0x80
+
+#CHECK: xsmerge2t3uqm 4, 5, 7
+0xec,0x85,0x3a,0xc8
+
+#CHECK: xsmerge3t1uqm 4, 5, 7
+0xec,0x85,0x3b,0xc8
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 9cefe2451b0e3..e52e6dfb9482c 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -267,3 +267,60 @@
#CHECK: xvmulhuh 4, 5, 7
0xd0,0x3b,0x85,0xf0
+
+#CHECK: xxmulmul 8, 3, 4, 2
+0x08,0x22,0x03,0xed
+
+#CHECK: xxmulmulhiadd 8, 3, 4, 1, 0, 1
+0x48,0x25,0x03,0xed
+
+#CHECK: xxmulmulloadd 8, 3, 4, 1, 0
+0x88,0x22,0x03,0xed
+
+#CHECK: xxssumudm 8, 3, 4, 1
+0xc8,0x24,0x03,0xed
+
+#CHECK: xxssumudmc 8, 3, 4, 1
+0xc8,0x25,0x03,0xed
+
+#CHECK: xxssumudmcext 8, 3, 4, 6, 0
+0x00,0x00,0x00,0x05,0xa0,0x21,0x03,0x89
+
+#CHECK: xsaddadduqm 4, 5, 7
+0x00,0x3b,0x85,0xec
+
+#CHECK: xsaddaddsuqm 4, 5, 7
+0x40,0x3b,0x85,0xec
+
+#CHECK: xsrebase2t1uqm 4, 5, 7
+0x88,0x3c,0x85,0xec
+
+#CHECK: xsrebase2t2uqm 4, 5, 7
+0x88,0x3d,0x85,0xec
+
+#CHECK: xsrebase2t3uqm 4, 5, 7
+0x88,0x3e,0x85,0xec
+
+#CHECK: xsrebase2t4uqm 4, 5, 7
+0xc8,0x3e,0x85,0xec
+
+#CHECK: xsrebase3t1uqm 4, 5, 7
+0x88,0x3f,0x85,0xec
+
+#CHECK: xsrebase3t2uqm 4, 5, 7
+0xc8,0x3f,0x85,0xec
+
+#CHECK: xsrebase3t3uqm 4, 5, 7
+0x18,0x3e,0x85,0xec
+
+#CHECK: xsmerge2t1uqm 4, 5, 7
+0x40,0x3f,0x85,0xec
+
+#CHECK: xsmerge2t2uqm 4, 5, 7
+0x80,0x3f,0x85,0xec
+
+#CHECK: xsmerge2t3uqm 4, 5, 7
+0xc8,0x3a,0x85,0xec
+
+#CHECK: xsmerge3t1uqm 4, 5, 7
+0xc8,0x3b,0x85,0xec
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index f01d6fa697d89..480478dddb0f4 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -386,3 +386,81 @@
xvmulhuh 4, 5, 7
#CHECK-BE: xvmulhuh 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0xd0]
#CHECK-LE: xvmulhuh 4, 5, 7 # encoding: [0xd0,0x3b,0x85,0xf0]
+
+ xxmulmul 8, 3, 4, 2
+#CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08]
+#CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed]
+
+ xxmulmulhiadd 8, 3, 4, 1, 0, 1
+#CHECK-BE: xxmulmulhiadd 8, 3, 4, 1, 0, 1 # encoding: [0xed,0x03,0x25,0x48]
+#CHECK-LE: xxmulmulhiadd 8, 3, 4, 1, 0, 1 # encoding: [0x48,0x25,0x03,0xed]
+
+ xxmulmulloadd 8, 3, 4, 1, 0
+#CHECK-BE: xxmulmulloadd 8, 3, 4, 1, 0 # encoding: [0xed,0x03,0x22,0x88]
+#CHECK-LE: xxmulmulloadd 8, 3, 4, 1, 0 # encoding: [0x88,0x22,0x03,0xed]
+
+ xxssumudm 8, 3, 4, 1
+#CHECK-BE: xxssumudm 8, 3, 4, 1 # encoding: [0xed,0x03,0x24,0xc8]
+#CHECK-LE: xxssumudm 8, 3, 4, 1 # encoding: [0xc8,0x24,0x03,0xed]
+
+ xxssumudmc 8, 3, 4, 1
+#CHECK-BE: xxssumudmc 8, 3, 4, 1 # encoding: [0xed,0x03,0x25,0xc8]
+#CHECK-LE: xxssumudmc 8, 3, 4, 1 # encoding: [0xc8,0x25,0x03,0xed]
+
+ xxssumudmcext 8, 3, 4, 6, 0
+# CHECK-BE: xxssumudmcext 8, 3, 4, 6, 0 # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME: 0x89,0x03,0x21,0xa0]
+# CHECK-LE: xxssumudmcext 8, 3, 4, 6, 0 # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME: 0xa0,0x21,0x03,0x89]
+
+ xsaddadduqm 4, 5, 7
+#CHECK-BE: xsaddadduqm 4, 5, 7 # encoding: [0xec,0x85,0x3b,0x00]
+#CHECK-LE: xsaddadduqm 4, 5, 7 # encoding: [0x00,0x3b,0x85,0xec]
+
+ xsaddaddsuqm 4, 5, 7
+#CHECK-BE: xsaddaddsuqm 4, 5, 7 # encoding: [0xec,0x85,0x3b,0x40]
+#CHECK-LE: xsaddaddsuqm 4, 5, 7 # encoding: [0x40,0x3b,0x85,0xec]
+
+ xsrebase2t1uqm 4, 5, 7
+#CHECK-BE: xsrebase2t1uqm 4, 5, 7 # encoding: [0xec,0x85,0x3c,0x88]
+#CHECK-LE: xsrebase2t1uqm 4, 5, 7 # encoding: [0x88,0x3c,0x85,0xec]
+
+ xsrebase2t2uqm 4, 5, 7
+#CHECK-BE: xsrebase2t2uqm 4, 5, 7 # encoding: [0xec,0x85,0x3d,0x88]
+#CHECK-LE: xsrebase2t2uqm 4, 5, 7 # encoding: [0x88,0x3d,0x85,0xec]
+
+ xsrebase2t3uqm 4, 5, 7
+#CHECK-BE: xsrebase2t3uqm 4, 5, 7 # encoding: [0xec,0x85,0x3e,0x88]
+#CHECK-LE: xsrebase2t3uqm 4, 5, 7 # encoding: [0x88,0x3e,0x85,0xec]
+
+ xsrebase2t4uqm 4, 5, 7
+#CHECK-BE: xsrebase2t4uqm 4, 5, 7 # encoding: [0xec,0x85,0x3e,0xc8]
+#CHECK-LE: xsrebase2t4uqm 4, 5, 7 # encoding: [0xc8,0x3e,0x85,0xec]
+
+ xsrebase3t1uqm 4, 5, 7
+#CHECK-BE: xsrebase3t1uqm 4, 5, 7 # encoding: [0xec,0x85,0x3f,0x88]
+#CHECK-LE: xsrebase3t1uqm 4, 5, 7 # encoding: [0x88,0x3f,0x85,0xec]
+
+ xsrebase3t2uqm 4, 5, 7
+#CHECK-BE: xsrebase3t2uqm 4, 5, 7 # encoding: [0xec,0x85,0x3f,0xc8]
+#CHECK-LE: xsrebase3t2uqm 4, 5, 7 # encoding: [0xc8,0x3f,0x85,0xec]
+
+ xsrebase3t3uqm 4, 5, 7
+#CHECK-BE: xsrebase3t3uqm 4, 5, 7 # encoding: [0xec,0x85,0x3e,0x18]
+#CHECK-LE: xsrebase3t3uqm 4, 5, 7 # encoding: [0x18,0x3e,0x85,0xec]
+
+ xsmerge2t1uqm 4, 5, 7
+#CHECK-BE: xsmerge2t1uqm 4, 5, 7 # encoding: [0xec,0x85,0x3f,0x40]
+#CHECK-LE: xsmerge2t1uqm 4, 5, 7 # encoding: [0x40,0x3f,0x85,0xec]
+
+ xsmerge2t2uqm 4, 5, 7
+#CHECK-BE: xsmerge2t2uqm 4, 5, 7 # encoding: [0xec,0x85,0x3f,0x80]
+#CHECK-LE: xsmerge2t2uqm 4, 5, 7 # encoding: [0x80,0x3f,0x85,0xec]
+
+ xsmerge2t3uqm 4, 5, 7
+#CHECK-BE: xsmerge2t3uqm 4, 5, 7 # encoding: [0xec,0x85,0x3a,0xc8]
+#CHECK-LE: xsmerge2t3uqm 4, 5, 7 # encoding: [0xc8,0x3a,0x85,0xec]
+
+ xsmerge3t1uqm 4, 5, 7
+#CHECK-BE: xsmerge3t1uqm 4, 5, 7 # encoding: [0xec,0x85,0x3b,0xc8]
+#CHECK-LE: xsmerge3t1uqm 4, 5, 7 # encoding: [0xc8,0x3b,0x85,0xec]
>From 28360e7482e653d35ba0d750113471f427fd3c38 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 26 Sep 2025 09:35:20 -0500
Subject: [PATCH 2/3] fix prefix instruction
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 87ace139bfeb0..33f4d410b671e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -274,6 +274,8 @@ class XX3Form_XTAB6_P<bits<7> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = XT{5};
}
+// Prefix instruction classes.
+
class 8RR_XX4Form_XTABC6_P<bits<6> opcode, bits<1> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
@@ -296,7 +298,7 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, bits<1> xo, dag OOL, dag IOL,
let Inst{43...47} = XA{4...0};
let Inst{48...52} = XB{4...0};
let Inst{53...57} = XC{4...0};
- let Inst{58} = xo;
+ let Inst{58} = 1
let Inst{59} = P;
let Inst{60} = XC{5};
let Inst{61} = XA{5};
@@ -304,11 +306,11 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, bits<1> xo, dag OOL, dag IOL,
let Inst{63} = XT{5};
}
-
//-------------------------- Instruction definitions -------------------------//
// Predicate combinations available:
// [IsISAFuture]
// [HasVSX, IsISAFuture]
+// [HasVSX, PrefixInstrs, IsISAFuture]
let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
@@ -437,11 +439,6 @@ let Predicates = [HasVSX, IsISAFuture] in {
def XXSSUMUDMC
: XX3Form_XTAB6_P<57, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),
"xxssumudmc $XT, $XA, $XB, $P", []>;
- def XXSSUMUDMCEXT
- : 8RR_XX4Form_XTABC6_P<34, 1, (outs vsrc:$XT),
- (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u1imm:$P),
- "xxssumudmcext $XT, $XA, $XB, $XC, $P",
- IIC_VecGeneral, []>;
def XSADDADDUQM
: XX3Form_XTAB6<59, 96, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xsaddadduqm $XT, $XA, $XB", []>;
@@ -483,6 +480,13 @@ let Predicates = [HasVSX, IsISAFuture] in {
"xsrebase3t3uqm $XT, $XA, $XB", []>;
}
+let Predicates = [HasVSX, PrefixInstrs, IsISAFuture] in {
+ def XXSSUMUDMCEXT
+ : 8RR_XX4Form_XTABC6_P<
+ 34, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u1imm:$P),
+ "xxssumudmcext $XT, $XA, $XB, $XC, $P", IIC_VecGeneral, []>;
+}
+
//---------------------------- Anonymous Patterns ----------------------------//
// Predicate combinations available:
>From 9464424960a3cc20831aa30ea3f5964f3946ad6c Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 26 Sep 2025 10:11:51 -0500
Subject: [PATCH 3/3] remove unnecessary xo field
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 33f4d410b671e..98da24deb5241 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -276,9 +276,9 @@ class XX3Form_XTAB6_P<bits<7> xo, dag OOL, dag IOL, string asmstr,
// Prefix instruction classes.
-class 8RR_XX4Form_XTABC6_P<bits<6> opcode, bits<1> xo, dag OOL, dag IOL,
- string asmstr, InstrItinClass itin, list<dag> pattern>
- : PI<1, opcode, OOL, IOL, asmstr, itin> {
+class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<6> XT;
bits<6> XA;
bits<6> XB;
@@ -290,15 +290,13 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, bits<1> xo, dag OOL, dag IOL,
// The prefix.
let Inst{6...7} = 1;
let Inst{8...11} = 0;
- let Inst{12...13} = 0;
- let Inst{14...31} = 0;
// The instruction.
let Inst{38...42} = XT{4...0};
let Inst{43...47} = XA{4...0};
let Inst{48...52} = XB{4...0};
let Inst{53...57} = XC{4...0};
- let Inst{58} = 1
+ let Inst{58} = 1;
let Inst{59} = P;
let Inst{60} = XC{5};
let Inst{61} = XA{5};
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