[llvm] [AMDGPU] Optimize rotate instruction selection patterns (PR #143551)

[Jay Foad via llvm-commits]

jayfoad wrote:

> **Third Approach**: Let ROTR be illegal, and FSHR be legal. In this scenario, ROTR is expanded in the legalizer pass, and later in the SDAG Combiner with a hook function for divergence checks for the AMDGPU target, it can be selectively combined. However, this leaves FSHR unexpanded in the legalizer. One approach was to create a custom legalizer for FSHR, making it selectively legal based on divergence information for SDAG, but this is impractical as operations should be either legal or illegal, adhering to LLVM coding paradigms. Another attempt was to expand FSHR into (SHL, SHR, OR pattern) in the combiner pass, but this contradicts the combiner's purpose, as it is meant to combine, not expand.

You might be right that "this contradicts the combiner's purpose" but I still think it could be made to work. Do you have a patch for this approach?

https://github.com/llvm/llvm-project/pull/143551