[llvm] 3257dc3 - [ARM] Remove `UnsafeFPMath` uses in code generation part (#160801)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 26 00:54:35 PDT 2025
Author: paperchalice
Date: 2025-09-26T15:54:30+08:00
New Revision: 3257dc35fe9ed872788e90c948cb4bb593b8fa05
URL: https://github.com/llvm/llvm-project/commit/3257dc35fe9ed872788e90c948cb4bb593b8fa05
DIFF: https://github.com/llvm/llvm-project/commit/3257dc35fe9ed872788e90c948cb4bb593b8fa05.diff
LOG: [ARM] Remove `UnsafeFPMath` uses in code generation part (#160801)
Factor out from #151275
Remove all UnsafeFPMath uses but ABI tags related part.
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/test/CodeGen/ARM/fnegs.ll
llvm/test/CodeGen/ARM/fnmscs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9a247bb5a83d9..78b706625a178 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5573,7 +5573,7 @@ static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
llvm_unreachable("Unknown VFP cmp argument!");
}
-/// OptimizeVFPBrcond - With nnan, it's legal to optimize some
+/// OptimizeVFPBrcond - With nnan and without daz, it's legal to optimize some
/// f32 and even f64 comparisons to integer ones.
SDValue
ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
@@ -5729,9 +5729,9 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
}
SDNodeFlags Flags = Op->getFlags();
- if ((getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
- (DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
- DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
+ if (Flags.hasNoNaNs() &&
+ DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
+ DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE() &&
(CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETNE ||
CC == ISD::SETUNE)) {
if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index f0592945b2051..3329beab63ddf 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -222,8 +222,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
const FeatureBitset &Bits = getFeatureBits();
if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
- (Options.UnsafeFPMath || isTargetDarwin() ||
- DM == DenormalMode::getPreserveSign()))
+ (isTargetDarwin() || DM == DenormalMode::getPreserveSign()))
HasNEONForFP = true;
if (isRWPI())
diff --git a/llvm/test/CodeGen/ARM/fnegs.ll b/llvm/test/CodeGen/ARM/fnegs.ll
index 435a600822e4d..6055b8f6dd93b 100644
--- a/llvm/test/CodeGen/ARM/fnegs.ll
+++ b/llvm/test/CodeGen/ARM/fnegs.ll
@@ -10,11 +10,11 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
; RUN: | FileCheck %s -check-prefix=CORTEXA8
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --denormal-fp-math=preserve-sign %s -o - \
; RUN: | FileCheck %s -check-prefix=CORTEXA8U
; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
-; RUN: | FileCheck %s -check-prefix=CORTEXA8U
+; RUN: | FileCheck %s -check-prefix=CORTEXA8U-DARWIN
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
; RUN: | FileCheck %s -check-prefix=CORTEXA9
@@ -41,7 +41,10 @@ entry:
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
; CORTEXA8U-LABEL: test1:
-; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
+; CORTEXA8U: vsub.f32 d{{.*}}, d{{.*}}, d{{.*}}
+
+; CORTEXA8U-DARWIN-LABEL: test1:
+; CORTEXA8U-DARWIN: vneg.f32 d{{.*}}, d{{.*}}
; CORTEXA9-LABEL: test1:
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
@@ -110,9 +113,13 @@ define <2 x float> @fneg_bitcast(i64 %i) {
; CORTEXA8-NOT: vneg.f32
; CORTEXA8U-LABEL: fneg_bitcast:
-; CORTEXA8U-DAG: eor r0, r0, #-2147483648
-; CORTEXA8U-DAG: eor r1, r1, #-2147483648
-; CORTEXA8U-NOT: vneg.f32
+; CORTEXA8U-DAG: vmov.i32 d{{.*}}, #0x80000000
+; CORTEXA8U-DAG: vsub.f32 d{{.*}}, d{{.*}}, d{{.*}}
+
+; CORTEXA8U-DARWIN-LABEL: fneg_bitcast:
+; CORTEXA8U-DARWIN-DAG: eor r0, r0, #-2147483648
+; CORTEXA8U-DARWIN-DAG: eor r1, r1, #-2147483648
+; CORTEXA8U-DARWIN-NOT: vneg.f32
; CORTEXA9-LABEL: fneg_bitcast:
; CORTEXA9-DAG: eor r0, r0, #-2147483648
diff --git a/llvm/test/CodeGen/ARM/fnmscs.ll b/llvm/test/CodeGen/ARM/fnmscs.ll
index 0fa878c0c2f49..49f9dcf32f544 100644
--- a/llvm/test/CodeGen/ARM/fnmscs.ll
+++ b/llvm/test/CodeGen/ARM/fnmscs.ll
@@ -13,11 +13,11 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic %s -o - \
; RUN: | FileCheck %s -check-prefix=A8
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --denormal-fp-math=preserve-sign %s -o - \
; RUN: | FileCheck %s -check-prefix=A8U
; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
-; RUN: | FileCheck %s -check-prefix=A8U
+; RUN: | FileCheck %s -check-prefix=A8U-DARWIN
define float @t1(float %acc, float %a, float %b) nounwind {
entry:
@@ -31,15 +31,20 @@ entry:
; NEON: vnmla.f32
; A8U-LABEL: t1:
-; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
-; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
+; A8U: vmov.i32 d{{[0-9]+}}, #0x80000000
+; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+
+; A8U-DARWIN-LABEL: t1:
+; A8U-DARWIN: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
+; A8U-DARWIN: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
; A8-LABEL: t1:
; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b
%1 = fsub float -0.0, %0
- %2 = fsub float %1, %acc
+ %2 = fsub float %1, %acc
ret float %2
}
@@ -55,8 +60,13 @@ entry:
; NEON: vnmla.f32
; A8U-LABEL: t2:
-; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
-; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
+; A8U: vmov.i32 d{{[0-9]+}}, #0x80000000
+; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+
+; A8U-DARWIN-LABEL: t2:
+; A8U-DARWIN: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
+; A8U-DARWIN: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
; A8-LABEL: t2:
; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
@@ -79,8 +89,12 @@ entry:
; NEON: vnmla.f64
; A8U-LABEL: t3:
-; A8U: vnmul.f64 d
; A8U: vsub.f64 d
+; A8U: vsub.f64 d
+
+; A8U-DARWIN-LABEL: t3:
+; A8U-DARWIN: vnmul.f64 d
+; A8U-DARWIN: vsub.f64 d
; A8-LABEL: t3:
; A8: vnmul.f64 d
@@ -103,8 +117,12 @@ entry:
; NEON: vnmla.f64
; A8U-LABEL: t4:
-; A8U: vnmul.f64 d
; A8U: vsub.f64 d
+; A8U: vsub.f64 d
+
+; A8U-DARWIN-LABEL: t4:
+; A8U-DARWIN: vnmul.f64 d
+; A8U-DARWIN: vsub.f64 d
; A8-LABEL: t4:
; A8: vnmul.f64 d
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