[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,86 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx942 --global-isel --new-reg-bank-select < %s -o - | FileCheck %s
+
+define i16 @add_i16(i16 %a, i16 %b) {
+; CHECK-LABEL: add_i16:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_add_u16_e32 v0, v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = add i16 %a, %b
+    ret i16 %c
+}
+
+define i32 @add_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: add_i32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_add_u32_e32 v0, v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = add i32 %a, %b
+    ret i32 %c
+}
+
+define <2 x i16> @add_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: add_v2i16:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_pk_add_u16 v0, v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = add <2 x i16> %a, %b
+    ret <2 x i16> %c
+}
+
+define i64 @add_i64(i64 %a, i64 %b) {
+; CHECK-LABEL: add_i64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    s_nop 1
+; CHECK-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = add i64 %a, %b
+    ret i64 %c
+}
+
+define i16 @sub_i16(i16 %a, i16 %b) {
+; CHECK-LABEL: sub_i16:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_sub_u16_e32 v0, v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = sub i16 %a, %b
+    ret i16 %c
+}
+
+define i32 @sub_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: sub_i32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_sub_u32_e32 v0, v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = sub i32 %a, %b
+    ret i32 %c
+}
+
+define <2 x i16> @sub_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: sub_v2i16:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_pk_sub_i16 v0, v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = sub <2 x i16> %a, %b
+    ret <2 x i16> %c
+}
+
+define i64 @sub_i64(i64 %a, i64 %b) {
+; CHECK-LABEL: sub_i64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    s_nop 1
+; CHECK-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+    %c = sub i64 %a, %b
+    ret i64 %c
+}
----------------
arsenm wrote:

The MIR tests do not replace the need for end to end IR tests. At this stage of development the end to end tests are more useful and easier to maintain. Unless testing a difficult edge case in MIR, there isn't much reason to directly test running the pass.

No, I meant we have comprehensive tests for xor already. By combinations I mean every permutation of relevant scalar types, vector types of all the relevant sizes, and every permutation of SGPR and VGPR inputs 

https://github.com/llvm/llvm-project/pull/159860