[llvm] [LoongArch][NFC] Pre-commit tests for vector sign and zero extensions (PR #160808)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 25 21:56:31 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-loongarch
Author: hev (heiher)
<details>
<summary>Changes</summary>
---
Patch is 116.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/160808.diff
4 Files Affected:
- (added) llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll (+1074)
- (added) llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll (+1206)
- (modified) llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll (+356-87)
- (modified) llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll (+283-73)
``````````diff
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
new file mode 100644
index 0000000000000..953e6c45608c0
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
@@ -0,0 +1,1074 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64
+
+define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i8_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.h $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
+; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
+; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr0
+; CHECK-NEXT: vslli.d $vr0, $vr0, 56
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i8>, ptr %ptr
+ %B = sext <2 x i8> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i16_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
+; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr0
+; CHECK-NEXT: vslli.d $vr0, $vr0, 48
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i16>, ptr %ptr
+ %B = sext <2 x i16> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_2i32_to_2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; LA32-NEXT: vslli.d $vr0, $vr0, 32
+; LA32-NEXT: vsrai.d $vr0, $vr0, 32
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_2i32_to_2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vshuf4i.w $vr0, $vr0, 16
+; LA64-NEXT: vslli.d $vr0, $vr0, 32
+; LA64-NEXT: vsrai.d $vr0, $vr0, 32
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <2 x i32>, ptr %ptr
+ %B = sext <2 x i32> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i8_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
+; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
+; CHECK-NEXT: vslli.w $vr0, $vr0, 24
+; CHECK-NEXT: vsrai.w $vr0, $vr0, 24
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i8>, ptr %ptr
+ %B = sext <4 x i8> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i8_to_4i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i8_to_4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: pcalau12i $a2, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: xvld $xr0, $a2, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 68
+; CHECK-NEXT: xvshuf.b $xr0, $xr0, $xr1, $xr0
+; CHECK-NEXT: xvslli.d $xr0, $xr0, 56
+; CHECK-NEXT: xvsrai.d $xr0, $xr0, 56
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i8>, ptr %ptr
+ %B = sext <4 x i8> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_4i16_to_4i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vilvl.h $vr0, $vr0, $vr0
+; LA32-NEXT: vslli.w $vr0, $vr0, 16
+; LA32-NEXT: vsrai.w $vr0, $vr0, 16
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_4i16_to_4i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vilvl.h $vr0, $vr0, $vr0
+; LA64-NEXT: vslli.w $vr0, $vr0, 16
+; LA64-NEXT: vsrai.w $vr0, $vr0, 16
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <4 x i16>, ptr %ptr
+ %B = sext <4 x i16> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i16_to_4i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_4i16_to_4i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI6_0)
+; LA32-NEXT: xvld $xr0, $a3, %pc_lo12(.LCPI6_0)
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: xvpermi.d $xr1, $xr1, 68
+; LA32-NEXT: xvshuf.h $xr0, $xr0, $xr1
+; LA32-NEXT: xvslli.d $xr0, $xr0, 48
+; LA32-NEXT: xvsrai.d $xr0, $xr0, 48
+; LA32-NEXT: xvst $xr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_4i16_to_4i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: pcalau12i $a2, %pc_hi20(.LCPI6_0)
+; LA64-NEXT: xvld $xr0, $a2, %pc_lo12(.LCPI6_0)
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: xvpermi.d $xr1, $xr1, 68
+; LA64-NEXT: xvshuf.h $xr0, $xr0, $xr1
+; LA64-NEXT: xvslli.d $xr0, $xr0, 48
+; LA64-NEXT: xvsrai.d $xr0, $xr0, 48
+; LA64-NEXT: xvst $xr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <4 x i16>, ptr %ptr
+ %B = sext <4 x i16> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i32_to_4i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_4i32_to_4i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a0, 0
+; LA32-NEXT: vextrins.w $vr1, $vr0, 2
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 2
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: vextrins.w $vr1, $vr0, 35
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 3
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vori.b $vr2, $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; LA32-NEXT: vextrins.w $vr2, $vr0, 33
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 1
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; LA32-NEXT: xvpermi.q $xr2, $xr1, 2
+; LA32-NEXT: xvst $xr2, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_4i32_to_4i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 2
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 3
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 0
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 1
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; LA64-NEXT: xvpermi.q $xr2, $xr1, 2
+; LA64-NEXT: xvst $xr2, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <4 x i32>, ptr %ptr
+ %B = sext <4 x i32> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_8i8_to_8i16:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vilvl.b $vr0, $vr0, $vr0
+; LA32-NEXT: vslli.h $vr0, $vr0, 8
+; LA32-NEXT: vsrai.h $vr0, $vr0, 8
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_8i8_to_8i16:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vilvl.b $vr0, $vr0, $vr0
+; LA64-NEXT: vslli.h $vr0, $vr0, 8
+; LA64-NEXT: vsrai.h $vr0, $vr0, 8
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = sext <8 x i8> %A to <8 x i16>
+ store <8 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i8_to_8i32(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_8i8_to_8i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI9_0)
+; LA32-NEXT: xvld $xr0, $a3, %pc_lo12(.LCPI9_0)
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: xvpermi.d $xr1, $xr1, 68
+; LA32-NEXT: xvshuf.b $xr0, $xr0, $xr1, $xr0
+; LA32-NEXT: xvslli.w $xr0, $xr0, 24
+; LA32-NEXT: xvsrai.w $xr0, $xr0, 24
+; LA32-NEXT: xvst $xr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_8i8_to_8i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: pcalau12i $a2, %pc_hi20(.LCPI9_0)
+; LA64-NEXT: xvld $xr0, $a2, %pc_lo12(.LCPI9_0)
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: xvpermi.d $xr1, $xr1, 68
+; LA64-NEXT: xvshuf.b $xr0, $xr0, $xr1, $xr0
+; LA64-NEXT: xvslli.w $xr0, $xr0, 24
+; LA64-NEXT: xvsrai.w $xr0, $xr0, 24
+; LA64-NEXT: xvst $xr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = sext <8 x i8> %A to <8 x i32>
+ store <8 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i8_to_8i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_8i8_to_8i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: xvpermi.d $xr1, $xr0, 68
+; LA32-NEXT: # kill: def $vr0 killed $vr0 killed $xr0
+; LA32-NEXT: pcalau12i $a2, %pc_hi20(.LCPI10_0)
+; LA32-NEXT: xvld $xr2, $a2, %pc_lo12(.LCPI10_0)
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vreplvei.w $vr0, $vr0, 1
+; LA32-NEXT: xvpermi.d $xr0, $xr0, 68
+; LA32-NEXT: xvshuf.b $xr0, $xr0, $xr0, $xr2
+; LA32-NEXT: xvslli.d $xr0, $xr0, 56
+; LA32-NEXT: xvsrai.d $xr0, $xr0, 56
+; LA32-NEXT: xvshuf.b $xr1, $xr0, $xr1, $xr2
+; LA32-NEXT: xvslli.d $xr1, $xr1, 56
+; LA32-NEXT: xvsrai.d $xr1, $xr1, 56
+; LA32-NEXT: xvst $xr1, $a1, 0
+; LA32-NEXT: xvst $xr0, $a1, 32
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_8i8_to_8i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: pcalau12i $a2, %pc_hi20(.LCPI10_0)
+; LA64-NEXT: xvld $xr0, $a2, %pc_lo12(.LCPI10_0)
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: vsrli.d $vr2, $vr1, 32
+; LA64-NEXT: xvpermi.d $xr2, $xr2, 68
+; LA64-NEXT: xvshuf.b $xr2, $xr0, $xr2, $xr0
+; LA64-NEXT: xvslli.d $xr2, $xr2, 56
+; LA64-NEXT: xvsrai.d $xr2, $xr2, 56
+; LA64-NEXT: xvpermi.d $xr1, $xr1, 68
+; LA64-NEXT: xvshuf.b $xr0, $xr0, $xr1, $xr0
+; LA64-NEXT: xvslli.d $xr0, $xr0, 56
+; LA64-NEXT: xvsrai.d $xr0, $xr0, 56
+; LA64-NEXT: xvst $xr0, $a1, 0
+; LA64-NEXT: xvst $xr2, $a1, 32
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = sext <8 x i8> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i16_to_8i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_8i16_to_8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: xvpermi.q $xr2, $xr1, 2
+; CHECK-NEXT: xvst $xr2, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = sext <8 x i16> %A to <8 x i32>
+ store <8 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_8i16_to_8i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a0, 0
+; LA32-NEXT: vpickve2gr.h $a0, $vr0, 2
+; LA32-NEXT: ext.w.h $a0, $a0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; LA32-NEXT: srai.w $a2, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 1
+; LA32-NEXT: vpickve2gr.h $a2, $vr0, 3
+; LA32-NEXT: ext.w.h $a2, $a2
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 2
+; LA32-NEXT: srai.w $a3, $a2, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 3
+; LA32-NEXT: vpickve2gr.h $a3, $vr0, 0
+; LA32-NEXT: ext.w.h $a3, $a3
+; LA32-NEXT: vinsgr2vr.w $vr2, $a3, 0
+; LA32-NEXT: vpickve2gr.h $a4, $vr0, 1
+; LA32-NEXT: ext.w.h $a4, $a4
+; LA32-NEXT: vinsgr2vr.w $vr2, $a4, 1
+; LA32-NEXT: srai.w $a3, $a3, 31
+; LA32-NEXT: vinsgr2vr.w $vr2, $a3, 1
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; LA32-NEXT: vinsgr2vr.w $vr2, $a4, 2
+; LA32-NEXT: vinsgr2vr.w $vr2, $a2, 3
+; LA32-NEXT: srai.w $a0, $a4, 31
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; LA32-NEXT: xvpermi.q $xr2, $xr1, 2
+; LA32-NEXT: vpickve2gr.h $a0, $vr0, 6
+; LA32-NEXT: ext.w.h $a0, $a0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; LA32-NEXT: srai.w $a2, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 1
+; LA32-NEXT: vpickve2gr.h $a2, $vr0, 7
+; LA32-NEXT: ext.w.h $a2, $a2
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 2
+; LA32-NEXT: srai.w $a3, $a2, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 3
+; LA32-NEXT: vpickve2gr.h $a3, $vr0, 4
+; LA32-NEXT: ext.w.h $a3, $a3
+; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 0
+; LA32-NEXT: vpickve2gr.h $a4, $vr0, 5
+; LA32-NEXT: ext.w.h $a4, $a4
+; LA32-NEXT: vinsgr2vr.w $vr3, $a4, 1
+; LA32-NEXT: srai.w $a3, $a3, 31
+; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 1
+; LA32-NEXT: vinsgr2vr.w $vr3, $a0, 2
+; LA32-NEXT: vinsgr2vr.w $vr3, $a4, 2
+; LA32-NEXT: vinsgr2vr.w $vr3, $a2, 3
+; LA32-NEXT: srai.w $a0, $a4, 31
+; LA32-NEXT: vinsgr2vr.w $vr3, $a0, 3
+; LA32-NEXT: xvpermi.q $xr3, $xr1, 2
+; LA32-NEXT: xvst $xr3, $a1, 32
+; LA32-NEXT: xvst $xr2, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_8i16_to_8i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 2
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 3
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 0
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 1
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; LA64-NEXT: xvpermi.q $xr2, $xr1, 2
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 6
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 7
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 4
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 5
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; LA64-NEXT: xvpermi.q $xr3, $xr1, 2
+; LA64-NEXT: xvst $xr3, $a1, 32
+; LA64-NEXT: xvst $xr2, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = sext <8 x i16> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i32_to_8i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_8i32_to_8i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvld $xr0, $a0, 0
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
+; LA32-NEXT: vextrins.w $vr2, $vr1, 2
+; LA32-NEXT: vpickve2gr.w $a0, $vr1, 2
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; LA32-NEXT: vextrins.w $vr2, $vr1, 35
+; LA32-NEXT: vpickve2gr.w $a0, $vr1, 3
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; LA32-NEXT: vpickve2gr.w $a0, $vr1, 0
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vori.b $vr3, $vr1, 0
+; LA32-NEXT: vinsgr2vr.w $vr3, $a0, 1
+; LA32-NEXT: vextrins.w $vr3, $vr1, 33
+; LA32-NEXT: vpickve2gr.w $a0, $vr1, 1
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr3, $a0, 3
+; LA32-NEXT: xvpermi.q $xr3, $xr2, 2
+; LA32-NEXT: vextrins.w $vr1, $vr0, 2
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 2
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: vextrins.w $vr1, $vr0, 35
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 3
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vori.b $vr2, $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; LA32-NEXT: vextrins.w $vr2, $vr0, 33
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 1
+; LA32-NEXT: srai.w $a0, $a0, 31
+; LA32-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; LA32-NEXT: xvpermi.q $xr2, $xr1, 2
+; LA32-NEXT: xvst $xr2, $a1, 0
+; LA32-NEXT: xvst $xr3, $a1, 32
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_8i32_to_8i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a0, 0
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
+; LA64-NEXT: vpickve2gr.w $a0, $vr1, 2
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr1, 3
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; LA64-NEXT: vpickve2gr.w $a0, $vr1, 0
+; LA64-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr1, 1
+; LA64-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; LA64-NEXT: xvpermi.q $xr3, $xr2, 2
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 2
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 3
+; LA64-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 0
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 1
+; LA64-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; LA64-NEXT: xvpermi.q $xr2, $xr1, 2
+; LA64-NEXT: xvst $xr2, $a1, 0
+; LA64-NEXT: xvst $xr3, $a1, 32
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i32>, ptr %ptr
+ %B = sext <8 x i32> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 7
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
+; CH...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/160808
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