[llvm] [RISCV] Update SiFive7's scheduling models with their optimizations on permutation instructions (PR #160763)

[Pengcheng Wang via llvm-commits]

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@@ -169,6 +169,64 @@ class SiFive7GetOrderedReductionCycles<string mx, int sew, int VLEN> {
   int c = !mul(6, VLUpperBound);
 }
 
+class isSingleDLEN<string mx> {
+  bit c = !or(!eq(mx, "MF2"), !or(!eq(mx, "MF4"), !eq(mx, "MF8")));
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wangpc-pp wrote:

This assumes `DLen` is always half of `VLen`. Is this true for all X-series cores?

https://github.com/llvm/llvm-project/pull/160763