[llvm] [InstCombine] Rotate transformation port from SelectionDAG to InstCombine (PR #160628)

[Axel Sorenson via llvm-commits]

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@@ -2405,6 +2405,23 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
               matchBSwapOrBitReverse(*II, /*MatchBSwaps*/ true,
                                      /*MatchBitReversals*/ true))
         return BitOp;
+
+      // R = fshl(X, X, C2)
+      // fshl(R, R, C1) --> fshl(X, X, (C1 + C2) % bitsize)
+      Value *InnerOp;
+      Constant *ShAmtInnerC;
+      if (match(Op0, m_FShl(m_Value(InnerOp), m_Deferred(InnerOp),
+                            m_ImmConstant(ShAmtInnerC))) &&
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axelcool1234 wrote:

Thanks for the suggestion. I'm still pretty new to LLVM here. Could you explain what this change does?

https://github.com/llvm/llvm-project/pull/160628