[llvm] 9652dc9 - [RISCV][test] Regenerate fpr-gpr-copy-rv64.ll

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2025-09-25T13:12:36+01:00
New Revision: 9652dc931be6598c441c7dc8f50c1fcb967c2410

URL: https://github.com/llvm/llvm-project/commit/9652dc931be6598c441c7dc8f50c1fcb967c2410
DIFF: https://github.com/llvm/llvm-project/commit/9652dc931be6598c441c7dc8f50c1fcb967c2410.diff

LOG: [RISCV][test] Regenerate fpr-gpr-copy-rv64.ll

It was missing RV64I lines for `fadd_f32`.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll
index 287bbbad6d52d..2a2abbdf9fa35 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll
@@ -30,6 +30,13 @@ define float @fadd_f32(float %x, float %y) {
 ; RV32I-NEXT:    fadd.d fa5, fa5, fa4
 ; RV32I-NEXT:    fmv.x.d a0, fa5
 ; RV32I-NEXT:    ret
+; RV64I-LABEL: fadd_f32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    fmv.w.x fa5, a0
+; RV64I-NEXT:    fmv.w.x fa4, a1
+; RV64I-NEXT:    fadd.s fa5, fa5, fa4
+; RV64I-NEXT:    fmv.x.w a0, fa5
+; RV64I-NEXT:    ret
   %a = fadd float %x, %y
   ret float %a
 }