[llvm] [LoongArch] Enable more vector tests for 32-bit target (PR #160656)

[via llvm-commits]

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@@ -1128,10 +1131,12 @@ SDValue LoongArchTargetLowering::lowerBITREVERSE(SDValue Op,
   SmallVector<SDValue, 8> Ops;
   for (unsigned int i = 0; i < NewEltNum; i++) {
     SDValue Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i64, NewSrc,
-                             DAG.getConstant(i, DL, MVT::i64));
+                             DAG.getConstant(i, DL, Subtarget.getGRLenVT()));
     unsigned RevOp = (ResTy == MVT::v16i8 || ResTy == MVT::v32i8)
                          ? (unsigned)LoongArchISD::BITREV_8B
                          : (unsigned)ISD::BITREVERSE;
+    if (!Subtarget.is64Bit() && RevOp == LoongArchISD::BITREV_8B)
+      return SDValue();
----------------
zhaoqi5 wrote:

I prefer move this ahead to avoid unnecesary `getNode()`.

This can be used:

```
// LoongArchISD::BITREV_8B is not supported on LA32.
if (!Subtarget.is64Bit() && (ResTy == MVT::v16i8 || ResTy == MVT::v32i8))
  return SDValue();
```

https://github.com/llvm/llvm-project/pull/160656