[llvm] [X86][GlobalISel] Added support for llvm.set.rounding (PR #156591)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 25 03:54:19 PDT 2025
================
@@ -859,6 +863,133 @@ bool X86LegalizerInfo::legalizeGETROUNDING(MachineInstr &MI,
return true;
}
+bool X86LegalizerInfo::legalizeSETROUNDING(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ LegalizerHelper &Helper) const {
+ MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+ MachineFunction &MF = MIRBuilder.getMF();
+ Register Src = MI.getOperand(0).getReg();
+ const LLT s8 = LLT::scalar(8);
+ const LLT s16 = LLT::scalar(16);
+ const LLT s32 = LLT::scalar(32);
+
+ // Allocate stack slot for control word and MXCSR (4 bytes).
+ int MemSize = 4;
+ Align Alignment = Align(4);
+ MachinePointerInfo PtrInfo;
+ auto StackTemp = Helper.createStackTemporary(TypeSize::getFixed(MemSize),
+ Alignment, PtrInfo);
+ Register StackPtr = StackTemp.getReg(0);
+
+ auto StoreMMO =
+ MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore, 2, Align(2));
+ MIRBuilder.buildInstr(X86::G_FNSTCW16)
+ .addUse(StackPtr)
+ .addMemOperand(StoreMMO);
+
+ auto LoadMMO =
+ MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad, 2, Align(2));
+ auto CWD16 = MIRBuilder.buildLoad(s16, StackPtr, *LoadMMO);
+
+ // Clear RM field (bits 11:10)
+ auto ClearedCWD =
+ MIRBuilder.buildAnd(s16, CWD16, MIRBuilder.buildConstant(s16, 0xf3ff));
+
+ // Check if Src is a constant
+ auto *SrcDef = MRI.getVRegDef(Src);
+ Register RMBits;
+ Register MXCSRRMBits;
+
+ if (SrcDef && SrcDef->getOpcode() == TargetOpcode::G_CONSTANT) {
+ uint64_t RM = getIConstantFromReg(Src, MRI).getZExtValue();
+ int FieldVal = X86::getRoundingModeX86(RM);
+
+ if (FieldVal == X86::rmInvalid) {
+ LLVMContext &C = MF.getFunction().getContext();
+ C.diagnose(DiagnosticInfoUnsupported(
+ MF.getFunction(), "rounding mode is not supported by X86 hardware",
----------------
JaydeepChauhan14 wrote:
Done
https://github.com/llvm/llvm-project/pull/156591
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