[llvm] dfc8854 - [LoongArch][NFC] Pre-commit tests for `[x]vadda.{b/h/w/d}`
Qi Zhao via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 25 02:07:01 PDT 2025
Author: Qi Zhao
Date: 2025-09-25T17:04:52+08:00
New Revision: dfc88549b0c2da7ea9d9c3cba9a08811e3e56f8a
URL: https://github.com/llvm/llvm-project/commit/dfc88549b0c2da7ea9d9c3cba9a08811e3e56f8a
DIFF: https://github.com/llvm/llvm-project/commit/dfc88549b0c2da7ea9d9c3cba9a08811e3e56f8a.diff
LOG: [LoongArch][NFC] Pre-commit tests for `[x]vadda.{b/h/w/d}`
Added:
llvm/test/CodeGen/LoongArch/lasx/ir-instruction/adda.ll
llvm/test/CodeGen/LoongArch/lsx/ir-instruction/adda.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/adda.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/adda.ll
new file mode 100644
index 0000000000000..e66a15291fb18
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/adda.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define void @vadda_b(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvneg.b $xr2, $xr0
+; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr2
+; CHECK-NEXT: xvneg.b $xr2, $xr1
+; CHECK-NEXT: xvmax.b $xr1, $xr1, $xr2
+; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <32 x i8>, ptr %a
+ %vb = load <32 x i8>, ptr %b
+ %conda = icmp slt <32 x i8> %va, zeroinitializer
+ %nega = sub <32 x i8> zeroinitializer, %va
+ %absa = select <32 x i1> %conda, <32 x i8> %nega, <32 x i8> %va
+ %condb = icmp slt <32 x i8> %vb, zeroinitializer
+ %negb = sub <32 x i8> zeroinitializer, %vb
+ %absb = select <32 x i1> %condb, <32 x i8> %negb, <32 x i8> %vb
+ %add = add <32 x i8> %absa, %absb
+ store <32 x i8> %add, ptr %res
+ ret void
+}
+
+define void @vadda_h(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvneg.h $xr2, $xr0
+; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr2
+; CHECK-NEXT: xvneg.h $xr2, $xr1
+; CHECK-NEXT: xvmax.h $xr1, $xr1, $xr2
+; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <16 x i16>, ptr %a
+ %vb = load <16 x i16>, ptr %b
+ %conda = icmp slt <16 x i16> %va, zeroinitializer
+ %nega = sub <16 x i16> zeroinitializer, %va
+ %absa = select <16 x i1> %conda, <16 x i16> %nega, <16 x i16> %va
+ %condb = icmp slt <16 x i16> %vb, zeroinitializer
+ %negb = sub <16 x i16> zeroinitializer, %vb
+ %absb = select <16 x i1> %condb, <16 x i16> %negb, <16 x i16> %vb
+ %add = add <16 x i16> %absa, %absb
+ store <16 x i16> %add, ptr %res
+ ret void
+}
+
+define void @vadda_w(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_w:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvneg.w $xr2, $xr0
+; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr2
+; CHECK-NEXT: xvneg.w $xr2, $xr1
+; CHECK-NEXT: xvmax.w $xr1, $xr1, $xr2
+; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <8 x i32>, ptr %a
+ %vb = load <8 x i32>, ptr %b
+ %conda = icmp slt <8 x i32> %va, zeroinitializer
+ %nega = sub <8 x i32> zeroinitializer, %va
+ %absa = select <8 x i1> %conda, <8 x i32> %nega, <8 x i32> %va
+ %condb = icmp slt <8 x i32> %vb, zeroinitializer
+ %negb = sub <8 x i32> zeroinitializer, %vb
+ %absb = select <8 x i1> %condb, <8 x i32> %negb, <8 x i32> %vb
+ %add = add <8 x i32> %absa, %absb
+ store <8 x i32> %add, ptr %res
+ ret void
+}
+
+define void @vadda_d(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvneg.d $xr2, $xr0
+; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr2
+; CHECK-NEXT: xvneg.d $xr2, $xr1
+; CHECK-NEXT: xvmax.d $xr1, $xr1, $xr2
+; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <4 x i64>, ptr %a
+ %vb = load <4 x i64>, ptr %b
+ %conda = icmp slt <4 x i64> %va, zeroinitializer
+ %nega = sub <4 x i64> zeroinitializer, %va
+ %absa = select <4 x i1> %conda, <4 x i64> %nega, <4 x i64> %va
+ %condb = icmp slt <4 x i64> %vb, zeroinitializer
+ %negb = sub <4 x i64> zeroinitializer, %vb
+ %absb = select <4 x i1> %condb, <4 x i64> %negb, <4 x i64> %vb
+ %add = add <4 x i64> %absa, %absb
+ store <4 x i64> %add, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/adda.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/adda.ll
new file mode 100644
index 0000000000000..2bd0b597d79ac
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/adda.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define void @vadda_b(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vneg.b $vr2, $vr0
+; CHECK-NEXT: vmax.b $vr0, $vr0, $vr2
+; CHECK-NEXT: vneg.b $vr2, $vr1
+; CHECK-NEXT: vmax.b $vr1, $vr1, $vr2
+; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <16 x i8>, ptr %a
+ %vb = load <16 x i8>, ptr %b
+ %conda = icmp slt <16 x i8> %va, zeroinitializer
+ %nega = sub <16 x i8> zeroinitializer, %va
+ %absa = select <16 x i1> %conda, <16 x i8> %nega, <16 x i8> %va
+ %condb = icmp slt <16 x i8> %vb, zeroinitializer
+ %negb = sub <16 x i8> zeroinitializer, %vb
+ %absb = select <16 x i1> %condb, <16 x i8> %negb, <16 x i8> %vb
+ %add = add <16 x i8> %absa, %absb
+ store <16 x i8> %add, ptr %res
+ ret void
+}
+
+define void @vadda_h(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vneg.h $vr2, $vr0
+; CHECK-NEXT: vmax.h $vr0, $vr0, $vr2
+; CHECK-NEXT: vneg.h $vr2, $vr1
+; CHECK-NEXT: vmax.h $vr1, $vr1, $vr2
+; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <8 x i16>, ptr %a
+ %vb = load <8 x i16>, ptr %b
+ %conda = icmp slt <8 x i16> %va, zeroinitializer
+ %nega = sub <8 x i16> zeroinitializer, %va
+ %absa = select <8 x i1> %conda, <8 x i16> %nega, <8 x i16> %va
+ %condb = icmp slt <8 x i16> %vb, zeroinitializer
+ %negb = sub <8 x i16> zeroinitializer, %vb
+ %absb = select <8 x i1> %condb, <8 x i16> %negb, <8 x i16> %vb
+ %add = add <8 x i16> %absa, %absb
+ store <8 x i16> %add, ptr %res
+ ret void
+}
+
+define void @vadda_w(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_w:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vneg.w $vr2, $vr0
+; CHECK-NEXT: vmax.w $vr0, $vr0, $vr2
+; CHECK-NEXT: vneg.w $vr2, $vr1
+; CHECK-NEXT: vmax.w $vr1, $vr1, $vr2
+; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <4 x i32>, ptr %a
+ %vb = load <4 x i32>, ptr %b
+ %conda = icmp slt <4 x i32> %va, zeroinitializer
+ %nega = sub <4 x i32> zeroinitializer, %va
+ %absa = select <4 x i1> %conda, <4 x i32> %nega, <4 x i32> %va
+ %condb = icmp slt <4 x i32> %vb, zeroinitializer
+ %negb = sub <4 x i32> zeroinitializer, %vb
+ %absb = select <4 x i1> %condb, <4 x i32> %negb, <4 x i32> %vb
+ %add = add <4 x i32> %absa, %absb
+ store <4 x i32> %add, ptr %res
+ ret void
+}
+
+define void @vadda_d(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: vadda_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vneg.d $vr2, $vr0
+; CHECK-NEXT: vmax.d $vr0, $vr0, $vr2
+; CHECK-NEXT: vneg.d $vr2, $vr1
+; CHECK-NEXT: vmax.d $vr1, $vr1, $vr2
+; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %va = load <2 x i64>, ptr %a
+ %vb = load <2 x i64>, ptr %b
+ %conda = icmp slt <2 x i64> %va, zeroinitializer
+ %nega = sub <2 x i64> zeroinitializer, %va
+ %absa = select <2 x i1> %conda, <2 x i64> %nega, <2 x i64> %va
+ %condb = icmp slt <2 x i64> %vb, zeroinitializer
+ %negb = sub <2 x i64> zeroinitializer, %vb
+ %absb = select <2 x i1> %condb, <2 x i64> %negb, <2 x i64> %vb
+ %add = add <2 x i64> %absa, %absb
+ store <2 x i64> %add, ptr %res
+ ret void
+}
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