[llvm] [MachineOutliner] Don't outline ADRP pair to avoid incorrect ICF (PR #160232)

David Green via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 25 01:49:06 PDT 2025


================
@@ -10179,11 +10179,33 @@ AArch64InstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
       return outliner::InstrType::Illegal;
   }
 
-  // Special cases for instructions that can always be outlined, but will fail
-  // the later tests. e.g, ADRPs, which are PC-relative use LR, but can always
-  // be outlined because they don't require a *specific* value to be in LR.
-  if (MI.getOpcode() == AArch64::ADRP)
+  // An ADRP instruction referencing a GOT should not be outlined.
----------------
davemgreen wrote:

I think they will often be laid out next to one another, so if we need to check that the next instruction is a adrp/add/etc then it should be quick to check. They are not always guaranteed to be next to one another though, in case the check fails. In which case it is probably fine to bail out.

If there are no candidates that ever mark one of the adrp/add individually as outlinable, would it ever be possible to outline a single instruction from them? That might not be the most reliable solution though.

> It appears that code is also going to prevent outlining of both HI/LO as a whole sequence and is buggy?

Maybe just a little inefficient? I'm not sure how much is lost from not outlining adrp+adds. If it is very little then marking them always invalid could be fine.

https://github.com/llvm/llvm-project/pull/160232


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