[llvm] [RISCV] Add commutative support for Qualcomm uC Xqcicm extension (PR #160653)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 25 00:02:45 PDT 2025
https://github.com/hchandel updated https://github.com/llvm/llvm-project/pull/160653
>From d51822835707bc7f6edb1e2499b9df06b1f34ce3 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 18 Sep 2025 12:06:27 +0530
Subject: [PATCH 1/6] Add commutative support for Xqcicm
Change-Id: Ib243360b22cb46580d5395645162f0cb1a8c6439
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 11 +++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 4 ++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 2723229859a55..6398f0b5f57f9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3742,6 +3742,9 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
return false;
// Operands 1 and 2 are commutable, if we switch the opcode.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
+ case RISCV::QC_MVEQ:
+ case RISCV::QC_MVNE:
+ return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 4);
case RISCV::TH_MULA:
case RISCV::TH_MULAW:
case RISCV::TH_MULAH:
@@ -3954,6 +3957,14 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
+ case RISCV::QC_MVEQ:
+ case RISCV::QC_MVNE: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVEQ ? RISCV::QC_MVNE
+ : RISCV::QC_MVEQ));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
case RISCV::PseudoCCMOVGPRNoX0:
case RISCV::PseudoCCMOVGPR: {
// CCMOV can be commuted by inverting the condition.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 9e3eb1c03fb37..b3121767f135e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -561,7 +561,7 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes
let Inst{31-25} = {simm, funct2};
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCIMVCC<bits<3> funct3, string opcodestr>
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
@@ -569,7 +569,7 @@ class QCIMVCC<bits<3> funct3, string opcodestr>
let Constraints = "$rd = $rd_wb";
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
>From 1468d4422cd2593d9c64f7fdb669a4f22e1266c8 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Wed, 24 Sep 2025 08:30:01 +0530
Subject: [PATCH 2/6] Add changes for commutative support in Xqcicm
Change-Id: I92b36c80c6cbb4bbbec19b672edb6e4a03ed0f32
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 50 ++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a771e489e0d1c..77649b3340346 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3764,6 +3764,16 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
case RISCV::QC_MVEQ:
case RISCV::QC_MVNE:
+ case RISCV::QC_MVLT:
+ case RISCV::QC_MVGE:
+ case RISCV::QC_MVLTU:
+ case RISCV::QC_MVGEU:
+ case RISCV::QC_MVEQI:
+ case RISCV::QC_MVNEI:
+ case RISCV::QC_MVLTI:
+ case RISCV::QC_MVGEI:
+ case RISCV::QC_MVLTUI:
+ case RISCV::QC_MVGEUI:
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 4);
case RISCV::TH_MULA:
case RISCV::TH_MULAW:
@@ -3985,6 +3995,46 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
+ case RISCV::QC_MVLT:
+ case RISCV::QC_MVGE: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLT ? RISCV::QC_MVGE
+ : RISCV::QC_MVLT));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
+ case RISCV::QC_MVLTU:
+ case RISCV::QC_MVGEU: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLTU ? RISCV::QC_MVGEU
+ : RISCV::QC_MVLTU));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
+ case RISCV::QC_MVEQI:
+ case RISCV::QC_MVNEI: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVEQI ? RISCV::QC_MVNEI
+ : RISCV::QC_MVEQI));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
+ case RISCV::QC_MVLTI:
+ case RISCV::QC_MVGEI: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLTI ? RISCV::QC_MVGEI
+ : RISCV::QC_MVLTI));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
+ case RISCV::QC_MVLTUI:
+ case RISCV::QC_MVGEUI: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLTUI ? RISCV::QC_MVGEUI
+ : RISCV::QC_MVLTUI));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
case RISCV::PseudoCCMOVGPRNoX0:
case RISCV::PseudoCCMOVGPR: {
// CCMOV can be commuted by inverting the condition.
>From a335dc6da25eca56397949b72d2e532971c9a244 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Wed, 24 Sep 2025 19:46:25 +0530
Subject: [PATCH 3/6] fixup! Add getReverseOpcode function
Change-Id: I1e0efe80c4281418fc5b84ca1273eb8f3b4016d4
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 74 ++++++++++++------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 77649b3340346..924c55ef3aa87 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1023,6 +1023,37 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
+static unsigned getReverseOpcode(unsigned Opcode){
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected Opcode");
+ case RISCV::QC_MVEQ:
+ return RISCV::QC_MVNE;
+ case RISCV::QC_MVNE:
+ return RISCV::QC_MVEQ;
+ case RISCV::QC_MVLT:
+ return RISCV::QC_MVGE;
+ case RISCV::QC_MVGE:
+ return RISCV::QC_MVLT;
+ case RISCV::QC_MVLTU:
+ return RISCV::QC_MVGEU;
+ case RISCV::QC_MVGEU:
+ return RISCV::QC_MVLTU;
+ case RISCV::QC_MVEQI:
+ return RISCV::QC_MVNEI;
+ case RISCV::QC_MVNEI:
+ return RISCV::QC_MVEQI;
+ case RISCV::QC_MVLTI:
+ return RISCV::QC_MVGEI;
+ case RISCV::QC_MVGEI:
+ return RISCV::QC_MVLTI;
+ case RISCV::QC_MVLTUI:
+ return RISCV::QC_MVGEUI;
+ case RISCV::QC_MVGEUI:
+ return RISCV::QC_MVLTUI;
+ }
+}
+
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
switch (SelectOpc) {
default:
@@ -3988,50 +4019,19 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
OpIdx2);
}
case RISCV::QC_MVEQ:
- case RISCV::QC_MVNE: {
- auto &WorkingMI = cloneIfNew(MI);
- WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVEQ ? RISCV::QC_MVNE
- : RISCV::QC_MVEQ));
- return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
- OpIdx2);
- }
+ case RISCV::QC_MVNE:
case RISCV::QC_MVLT:
- case RISCV::QC_MVGE: {
- auto &WorkingMI = cloneIfNew(MI);
- WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLT ? RISCV::QC_MVGE
- : RISCV::QC_MVLT));
- return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
- OpIdx2);
- }
+ case RISCV::QC_MVGE:
case RISCV::QC_MVLTU:
- case RISCV::QC_MVGEU: {
- auto &WorkingMI = cloneIfNew(MI);
- WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLTU ? RISCV::QC_MVGEU
- : RISCV::QC_MVLTU));
- return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
- OpIdx2);
- }
+ case RISCV::QC_MVGEU:
case RISCV::QC_MVEQI:
- case RISCV::QC_MVNEI: {
- auto &WorkingMI = cloneIfNew(MI);
- WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVEQI ? RISCV::QC_MVNEI
- : RISCV::QC_MVEQI));
- return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
- OpIdx2);
- }
+ case RISCV::QC_MVNEI:
case RISCV::QC_MVLTI:
- case RISCV::QC_MVGEI: {
- auto &WorkingMI = cloneIfNew(MI);
- WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLTI ? RISCV::QC_MVGEI
- : RISCV::QC_MVLTI));
- return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
- OpIdx2);
- }
+ case RISCV::QC_MVGEI:
case RISCV::QC_MVLTUI:
case RISCV::QC_MVGEUI: {
auto &WorkingMI = cloneIfNew(MI);
- WorkingMI.setDesc(get(MI.getOpcode() == RISCV::QC_MVLTUI ? RISCV::QC_MVGEUI
- : RISCV::QC_MVLTUI));
+ WorkingMI.setDesc(get(getReverseOpcode(MI.getOpcode())));
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
>From 8aa2e62371a97d0ac8d874303f13abdeef835314 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 25 Sep 2025 11:46:19 +0530
Subject: [PATCH 4/6] fixup! Precommit xqcicm.ll with 'mv's
Change-Id: Ib254085f0397e3dc2f31d9f1a23b1035483ea458
---
llvm/test/CodeGen/RISCV/xqcicm.ll | 265 ++++++++++++++++++++++++++++++
1 file changed, 265 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 1741be742323d..184697f19d337 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -898,3 +898,268 @@ entry:
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
+
+define i32 @select_cc_example_eq_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a2, a1, .LBB32_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mveq a3, a2, a1, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveq a3, a2, a1, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_lt_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_lt_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: blt a2, a1, .LBB33_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_lt_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvlt a3, a2, a1, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_lt_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlt a3, a2, a1, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp slt i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ge_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ge_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bge a2, a1, .LBB34_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB34_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ge_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvge a3, a2, a1, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ge_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvge a3, a2, a1, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp sge i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ult_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ult_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bltu a2, a1, .LBB35_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB35_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ult_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvltu a3, a2, a1, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltu a3, a2, a1, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp ult i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_uge_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_uge_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bgeu a2, a1, .LBB36_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB36_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_uge_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvgeu a3, a2, a1, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeu a3, a2, a1, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp uge i32 %x, %b
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_eq_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: beq a2, a1, .LBB37_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB37_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mveqi a3, a2, 11, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveqi a3, a2, 11, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_lt_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_lt_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: blt a2, a1, .LBB38_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB38_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_lt_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvlti a3, a2, 11, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_lt_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a2, 11, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp slt i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ge_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ge_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 10
+; RV32I-NEXT: blt a1, a2, .LBB39_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB39_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ge_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvgei a3, a2, 11, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ge_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a2, 11, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp sge i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ult_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ult_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: bltu a2, a1, .LBB40_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB40_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ult_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvltui a3, a2, 11, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a2, 11, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp ult i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_uge_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_uge_imm_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 10
+; RV32I-NEXT: bltu a1, a2, .LBB41_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB41_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_uge_imm_mv:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a2, 11, a0
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_imm_mv:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a2, 11, a0
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+entry:
+ %cmp = icmp uge i32 %x, 11
+ %sel = select i1 %cmp, i32 %a, i32 %y
+ ret i32 %sel
+}
>From 01ca3cbbc503b8ca9c2ad08a79a2b642297eec6b Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 25 Sep 2025 12:21:00 +0530
Subject: [PATCH 5/6] fixup! Add test changes
Change-Id: I61cb49361b8b9eb971e4786e33b1761e3f70fd2f
---
llvm/test/CodeGen/RISCV/xqcicm.ll | 316 ++++++++++++++----------------
1 file changed, 148 insertions(+), 168 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 184697f19d337..fb48301b1d8e8 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -23,15 +23,15 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32IXQCICM-LABEL: select_example:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: andi a0, a0, 1
-; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCICM-NEXT: mv a0, a1
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_example:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
@@ -52,14 +52,14 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
@@ -80,14 +80,14 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
@@ -108,14 +108,14 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
@@ -136,14 +136,14 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
@@ -164,14 +164,14 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, 11
@@ -192,14 +192,14 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 11, %a
@@ -220,14 +220,14 @@ define i32 @select_cc_example_sle(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, 11
@@ -248,14 +248,14 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 11, %a
@@ -276,14 +276,14 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 11
@@ -304,14 +304,14 @@ define i32 @select_cc_example_sgt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 11, %a
@@ -332,14 +332,14 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, 11
@@ -360,14 +360,14 @@ define i32 @select_cc_example_sge1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 11, %a
@@ -388,14 +388,14 @@ define i32 @select_cc_example_ule(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, 11
@@ -416,14 +416,14 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 11, %a
@@ -444,14 +444,14 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, 11
@@ -472,14 +472,14 @@ define i32 @select_cc_example_ugt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 11, %a
@@ -500,14 +500,14 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, 11
@@ -528,14 +528,14 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 11, %a
@@ -556,14 +556,14 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, 11
@@ -584,14 +584,14 @@ define i32 @select_cc_example_uge1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 11, %a
@@ -611,14 +611,14 @@ define i32 @select_cc_example_eq_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
@@ -638,14 +638,14 @@ define i32 @select_cc_example_ne_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
@@ -665,14 +665,14 @@ define i32 @select_cc_example_slt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, %b
@@ -692,14 +692,14 @@ define i32 @select_cc_example_sge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvge a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, %b
@@ -719,14 +719,14 @@ define i32 @select_cc_example_sgt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvge a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, %b
@@ -746,14 +746,14 @@ define i32 @select_cc_example_sle_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvge a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, %b
@@ -773,14 +773,14 @@ define i32 @select_cc_example_ugt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, %b
@@ -800,14 +800,14 @@ define i32 @select_cc_example_ult_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, %b
@@ -827,14 +827,14 @@ define i32 @select_cc_example_uge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, %b
@@ -854,14 +854,14 @@ define i32 @select_cc_example_ule_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, %b
@@ -883,15 +883,15 @@ define i32 @select_cc_example_ule_neg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-LABEL: select_cc_example_ule_neg:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: li a1, -10
-; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule_neg:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: li a1, -10
-; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, -11
@@ -910,14 +910,12 @@ define i32 @select_cc_example_eq_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveq a3, a2, a1, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvne a0, a2, a1, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveq a3, a2, a1, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvne a0, a2, a1, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %x, %b
@@ -936,14 +934,12 @@ define i32 @select_cc_example_lt_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_lt_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a3, a2, a1, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvge a0, a2, a1, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_lt_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlt a3, a2, a1, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a0, a2, a1, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %x, %b
@@ -962,14 +958,12 @@ define i32 @select_cc_example_ge_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ge_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvge a3, a2, a1, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlt a0, a2, a1, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ge_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvge a3, a2, a1, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlt a0, a2, a1, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %x, %b
@@ -988,14 +982,12 @@ define i32 @select_cc_example_ult_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a3, a2, a1, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeu a0, a2, a1, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltu a3, a2, a1, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a0, a2, a1, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %x, %b
@@ -1014,14 +1006,12 @@ define i32 @select_cc_example_uge_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeu a3, a2, a1, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltu a0, a2, a1, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeu a3, a2, a1, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltu a0, a2, a1, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %x, %b
@@ -1041,14 +1031,12 @@ define i32 @select_cc_example_eq_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq_imm_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a2, 11, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a0, a2, 11, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq_imm_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a2, 11, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a0, a2, 11, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %x, 11
@@ -1068,14 +1056,12 @@ define i32 @select_cc_example_lt_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_lt_imm_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a2, 11, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a0, a2, 11, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_lt_imm_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a2, 11, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a0, a2, 11, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %x, 11
@@ -1095,14 +1081,12 @@ define i32 @select_cc_example_ge_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ge_imm_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a2, 11, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a0, a2, 11, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ge_imm_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a2, 11, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a0, a2, 11, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %x, 11
@@ -1122,14 +1106,12 @@ define i32 @select_cc_example_ult_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult_imm_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a2, 11, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a0, a2, 11, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult_imm_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a2, 11, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a0, a2, 11, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %x, 11
@@ -1149,14 +1131,12 @@ define i32 @select_cc_example_uge_imm_mv(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_imm_mv:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a2, 11, a0
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a0, a2, 11, a3
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge_imm_mv:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a2, 11, a0
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a0, a2, 11, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %x, 11
>From c40dee4ac182f0539f34751ba31db500e02d367f Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 25 Sep 2025 12:31:33 +0530
Subject: [PATCH 6/6] fixup! clang format
Change-Id: I062552426237d36ef96559d05df982e4a7c3ac67
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 924c55ef3aa87..9ea98b9ac0d01 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1023,7 +1023,7 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
-static unsigned getReverseOpcode(unsigned Opcode){
+static unsigned getReverseOpcode(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected Opcode");
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