[llvm] [PowerPC] Implement Context Switch Instr mtlpl (PR #160593)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-powerpc

Author: Lei Huang (lei137)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/160593.diff


4 Files Affected:

- (modified) llvm/lib/Target/PowerPC/PPCInstrFuture.td (+17) 
- (modified) llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt (+3) 
- (modified) llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt (+3) 
- (modified) llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s (+4) 


``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 46cd8cd0a83b3..83177ccec69d6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -183,6 +183,20 @@ class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31} = XT{5};
 }
 
+class XForm_RBS5<bits<6> opCode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin, list<dag> pattern>
+    : I<opCode, OOL, IOL, asmstr, itin> {
+
+  bits<5> RB;
+  bits<5> RS;
+
+  let Pattern = pattern;
+
+  let Inst{6...10} = RS;
+  let Inst{16...20} = RB;
+  let Inst{21...30} = xo;
+}
+
 //-------------------------- Instruction definitions -------------------------//
 // Predicate combinations available:
 // [IsISAFuture]
@@ -192,6 +206,9 @@ let Predicates = [IsISAFuture] in {
   defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
                                  (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
                                  "$RT, $L, $RA, $RB", []>;
+  def MTLPL : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
+                         "mtlpl $RB, $RS", IIC_SprMTSPR, []>,
+              Requires<[IsPPC64]>;
 }
 
 let Predicates = [HasVSX, IsISAFuture] in {
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index a203c706fb44a..c26004649587f 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -243,3 +243,6 @@
 
 #CHECK: xxgfmul128gcm 7, 5, 4
 0xf0,0xe5,0x26,0xd0
+
+#CHECK: mtlpl 3, 4
+0x7c,0x80,0x1a,0x26
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 713015df90b91..d111281b0e211 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -237,3 +237,6 @@
 
 #CHECK: xxgfmul128gcm 7, 5, 4
 0xd0,0x26,0xe5,0xf0
+
+#CHECK: mtlpl 3, 4
+0x26,0x1a,0x80,0x7c
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 824716877d57f..95ba7d537c92a 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -346,3 +346,7 @@
            xxgfmul128gcm 7, 5, 4
 #CHECK-BE: xxgfmul128gcm 7, 5, 4          # encoding: [0xf0,0xe5,0x26,0xd0]
 #CHECK-LE: xxgfmul128gcm 7, 5, 4          # encoding: [0xd0,0x26,0xe5,0xf0]
+
+           mtlpl 3, 4
+#CHECK-BE: mtlpl 3, 4                     # encoding: [0x7c,0x80,0x1a,0x26]
+#CHECK-LE: mtlpl 3, 4                     # encoding: [0x26,0x1a,0x80,0x7c]

``````````

</details>


https://github.com/llvm/llvm-project/pull/160593