[llvm] [DAG] fix wrong type check in DAGCombiner::visitSRA (PR #153762)

[Matt Arsenault via llvm-commits]

================
@@ -10872,8 +10872,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
       // on that type, and the truncate to that type is both legal and free,
       // perform the transform.
       if ((ShiftAmt > 0) &&
-          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
-          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, TruncVT) &&
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arsenm wrote:

This amdgpu testcase hits this path:
```
define i64 @foo(i64 %x) {
  %shl = shl i64 %x, 22
  %sra = ashr i64 %shl, 32
  ret i64 %sra
}
```

But there's no net change in codegen after this change, probably because we have custom combines to hack out i64 shifts. Is the inner shift dropping flags that can be preserved? 

https://github.com/llvm/llvm-project/pull/153762