[llvm] [AMDGPU] Register allocation anti-hints to reduce MFMA hazard NOPs (PR #156943)

[Matt Arsenault via llvm-commits]

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@@ -209,6 +210,11 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
                        StringValue()); // Don't print out when it's empty.
     YamlIO.mapOptional("flags", Reg.RegisterFlags,
                        std::vector<FlowStringValue>());
+    if (!YamlIO.outputting() ||
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arsenm wrote:

This all needs dedicated MIR parsing tests in test/CodeGen/MIR, including error cases 

https://github.com/llvm/llvm-project/pull/156943