[llvm] [AMDGPU] Support `xor cond, -1` when lowering `BRCOND` (PR #160341)

[Stanislav Mekhanoshin via llvm-commits]

================
@@ -7540,17 +7540,34 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, SelectionDAG &DAG) const {
   SDNode *BR = nullptr;
   SDNode *SetCC = nullptr;
 
-  if (Intr->getOpcode() == ISD::SETCC) {
+  switch (Intr->getOpcode()) {
+  case ISD::SETCC: {
     // As long as we negate the condition everything is fine
     SetCC = Intr;
     Intr = SetCC->getOperand(0).getNode();
-
-  } else {
+    break;
+  }
+  case ISD::XOR: {
+    // Similar to SETCC, if we have (xor c, -1) or (xor -1, c), we will be fine.
----------------
rampitec wrote:

Canonical form is literal always RHS.

https://github.com/llvm/llvm-project/pull/160341