[llvm] 51a86e7 - [MCA][RISCV]Enable latency instrument on RISCV (#160063)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 23 09:50:38 PDT 2025
Author: Roman Belenov
Date: 2025-09-23T09:50:34-07:00
New Revision: 51a86e75ddf3eac3057c901bbe5e750dea62c7c1
URL: https://github.com/llvm/llvm-project/commit/51a86e75ddf3eac3057c901bbe5e750dea62c7c1
DIFF: https://github.com/llvm/llvm-project/commit/51a86e75ddf3eac3057c901bbe5e750dea62c7c1.diff
LOG: [MCA][RISCV]Enable latency instrument on RISCV (#160063)
Recently added latency customization
([PR](https://github.com/llvm/llvm-project/pull/155420)) does not work
on RISCV since it has target-specific InstrumentManager that overrides
default functionality. Added calls to base class to ensure that common
instruments (including latency customizer) are available.
Added:
llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s
Modified:
llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index ae44306170758..50730c697989d 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -18,6 +18,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/DebugLog.h"
#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
@@ -86,7 +87,8 @@ uint8_t RISCVSEWInstrument::getSEW() const {
bool RISCVInstrumentManager::supportsInstrumentType(
llvm::StringRef Type) const {
return Type == RISCVLMULInstrument::DESC_NAME ||
- Type == RISCVSEWInstrument::DESC_NAME;
+ Type == RISCVSEWInstrument::DESC_NAME ||
+ InstrumentManager::supportsInstrumentType(Type);
}
UniqueInstrument
@@ -94,8 +96,8 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc,
llvm::StringRef Data) {
if (Desc == RISCVLMULInstrument::DESC_NAME) {
if (!RISCVLMULInstrument::isDataValid(Data)) {
- LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
- << Data << '\n');
+ LDBG() << "RVCB: Bad data for instrument kind " << Desc << ": " << Data
+ << '\n';
return nullptr;
}
return std::make_unique<RISCVLMULInstrument>(Data);
@@ -103,23 +105,23 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc,
if (Desc == RISCVSEWInstrument::DESC_NAME) {
if (!RISCVSEWInstrument::isDataValid(Data)) {
- LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
- << Data << '\n');
+ LDBG() << "RVCB: Bad data for instrument kind " << Desc << ": " << Data
+ << '\n';
return nullptr;
}
return std::make_unique<RISCVSEWInstrument>(Data);
}
- LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc << '\n');
- return nullptr;
+ LDBG() << "RVCB: Creating default instrument for Desc: " << Desc << '\n';
+ return InstrumentManager::createInstrument(Desc, Data);
}
SmallVector<UniqueInstrument>
RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
if (Inst.getOpcode() == RISCV::VSETVLI ||
Inst.getOpcode() == RISCV::VSETIVLI) {
- LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: "
- << Inst << "\n");
+ LDBG() << "RVCB: Found VSETVLI and creating instrument for it: " << Inst
+ << "\n";
unsigned VTypeI = Inst.getOperand(2).getImm();
RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
@@ -250,8 +252,7 @@ unsigned RISCVInstrumentManager::getSchedClassID(
// Need LMUL or LMUL, SEW in order to override opcode. If no LMUL is provided,
// then no option to override.
if (!LI) {
- LLVM_DEBUG(
- dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
+ LDBG() << "RVCB: Did not use instrumentation to override Opcode.\n";
return SchedClassID;
}
uint8_t LMUL = LI->getLMUL();
@@ -313,22 +314,21 @@ unsigned RISCVInstrumentManager::getSchedClassID(
// Not a RVV instr
if (!VPOpcode) {
- LLVM_DEBUG(
- dbgs() << "RVCB: Could not find PseudoInstruction for Opcode "
- << MCII.getName(Opcode)
- << ", LMUL=" << (LI ? LI->getData() : "Unspecified")
- << ", SEW=" << (SI ? SI->getData() : "Unspecified")
- << ". Ignoring instrumentation and using original SchedClassID="
- << SchedClassID << '\n');
+ LDBG() << "RVCB: Could not find PseudoInstruction for Opcode "
+ << MCII.getName(Opcode)
+ << ", LMUL=" << (LI ? LI->getData() : "Unspecified")
+ << ", SEW=" << (SI ? SI->getData() : "Unspecified")
+ << ". Ignoring instrumentation and using original SchedClassID="
+ << SchedClassID << '\n';
return SchedClassID;
}
// Override using pseudo
- LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode "
- << MCII.getName(Opcode) << ", LMUL=" << LI->getData()
- << ", SEW=" << (SI ? SI->getData() : "Unspecified")
- << ". Overriding original SchedClassID=" << SchedClassID
- << " with " << MCII.getName(*VPOpcode) << '\n');
+ LDBG() << "RVCB: Found Pseudo Instruction for Opcode " << MCII.getName(Opcode)
+ << ", LMUL=" << LI->getData()
+ << ", SEW=" << (SI ? SI->getData() : "Unspecified")
+ << ". Overriding original SchedClassID=" << SchedClassID << " with "
+ << MCII.getName(*VPOpcode) << '\n';
return MCII.get(*VPOpcode).getSchedClass();
}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s
new file mode 100644
index 0000000000000..376038b2d3037
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s
@@ -0,0 +1,59 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 --timeline -iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-LATENCY 20
+add a0, a0, a0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 1
+# CHECK-NEXT: Total Cycles: 21
+# CHECK-NEXT: Total uOps: 1
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.05
+# CHECK-NEXT: IPC: 0.05
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 add a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
+# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
+# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
+# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
+# CHECK-NEXT: [4] - VLEN512SiFive7VA
+# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
+# CHECK-NEXT: [6] - VLEN512SiFive7VL
+# CHECK-NEXT: [7] - VLEN512SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - - 1.00 - - - - add a0, a0, a0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeE add a0, a0, a0
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add a0, a0, a0
More information about the llvm-commits
mailing list