[llvm] [DRAFT][RegisterCoalescer] Enable non-trivial rematerialization (PR #160153)

[Philip Reames via llvm-commits]

preames wrote:

> Another case I'm interested in that's nontrivial is rematerializing that requires rewriting the instruction. e.g. rematerializing only part of a value if only sub registers are demanded, or changing the use instruction to a different opcode based on register bank

Yeah, there's variants here we can explore once we get the virtual register use case handled properly and generically.  One I'm interested in is multiple instruction remat.  On RISC-V, we've got e.g. LUI+ADDI which is the canonical 32 bit constant materialization sequence, and is frequently macro fused into one op in hardware anyways.  It sucks we can't remat that today.  Another sub-category is the virtual register uses where we don't fit within the existing live interval of the use, but can trivially extend it.  Each sub-category is non-trivial and requires thought and care as we move through.  

https://github.com/llvm/llvm-project/pull/160153