[llvm] [llvm][RISCV] Don't merge pseudo selects with stack adjustment instr in between (PR #160105)

[Elizaveta Noskova via llvm-commits]

https://github.com/enoskova-sc updated https://github.com/llvm/llvm-project/pull/160105

>From dd47d7d38f85b44f434ef38db55134fc7d08bfd7 Mon Sep 17 00:00:00 2001
From: Elizaveta Noskova <elizaveta.noskova at syntacore.com>
Date: Thu, 18 Sep 2025 12:55:05 +0300
Subject: [PATCH] [llvm][RISCV] Don't merge pseudo selects with stack
 adjustment instr in between

When we have sequence of select pseudo instruction with stack adjustment instr in between,
we shouldn't apply the optimization, proposed here (https://reviews.llvm.org/D59355) for them,
because in that case on Finalize ISel function won't be marked as adjustsStack.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |  8 ++-
 .../select-pseudo-merge-with-stack-adj.ll     | 64 +++++++++++++++++++
 2 files changed, 70 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 542be1c20efc0..5698fc2d6f9f5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22190,6 +22190,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   // - They are debug instructions. Otherwise,
   // - They do not have side-effects, do not access memory and their inputs do
   //   not depend on the results of the select pseudo-instructions.
+  // - They don't adjust stack.
   // The TrueV/FalseV operands of the selects cannot depend on the result of
   // previous selects in the sequence.
   // These conditions could be further relaxed. See the X86 target for a
@@ -22218,6 +22219,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   SelectDests.insert(MI.getOperand(0).getReg());
 
   MachineInstr *LastSelectPseudo = &MI;
+  const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
+
   for (auto E = BB->end(), SequenceMBBI = MachineBasicBlock::iterator(MI);
        SequenceMBBI != E; ++SequenceMBBI) {
     if (SequenceMBBI->isDebugInstr())
@@ -22237,7 +22240,9 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
     }
     if (SequenceMBBI->hasUnmodeledSideEffects() ||
         SequenceMBBI->mayLoadOrStore() ||
-        SequenceMBBI->usesCustomInsertionHook())
+        SequenceMBBI->usesCustomInsertionHook() ||
+        TII.isFrameInstr(*SequenceMBBI) ||
+        SequenceMBBI->isStackAligningInlineAsm())
       break;
     if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) {
           return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
@@ -22245,7 +22250,6 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
       break;
   }
 
-  const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction::iterator I = ++BB->getIterator();
diff --git a/llvm/test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll b/llvm/test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll
new file mode 100644
index 0000000000000..f0941120fc806
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc %s -mtriple riscv32 -verify-machineinstrs -o - | FileCheck %s
+
+define i32 @test(i1 %arg_1, i32 %arg_2) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    .cfi_offset s1, -12
+; CHECK-NEXT:    andi s1, a0, 1
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv s0, a1
+; CHECK-NEXT:    bnez s1, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    li s0, 1
+; CHECK-NEXT:  .LBB0_2: # %entry
+; CHECK-NEXT:    li a1, 7
+; CHECK-NEXT:    call __udivsi3
+; CHECK-NEXT:    bnez s1, .LBB0_4
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    li a0, 3
+; CHECK-NEXT:  .LBB0_4: # %entry
+; CHECK-NEXT:    bnez s1, .LBB0_6
+; CHECK-NEXT:  # %bb.5: # %entry
+; CHECK-NEXT:    mv s0, a0
+; CHECK-NEXT:  .LBB0_6: # %entry
+; CHECK-NEXT:    li a0, 3
+; CHECK-NEXT:  .LBB0_7: # %body
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    addi s0, s0, 4
+; CHECK-NEXT:    bltu a0, s0, .LBB0_7
+; CHECK-NEXT:  # %bb.8: # %exit
+; CHECK-NEXT:    mv a0, s0
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+entry:
+  %sel_1 = select i1 %arg_1, i32 %arg_2, i32 1
+  %div = udiv i32 %arg_2, 7
+  %cond_1 = icmp ugt i32 %div, %sel_1
+  %sel_2 = select i1 %arg_1, i32 %div, i32 3
+  %sel = select i1 %arg_1, i32 %sel_1, i32 %sel_2
+  br label %body
+
+body:
+  %res = phi i32 [ %sel, %entry ], [ %add_loop, %body ]
+  %add_loop = add i32 4, %res
+  %cond_2 = icmp ugt i32 %add_loop, 3
+  br i1 %cond_2, label %body, label %exit
+
+exit:
+  ret i32 %add_loop
+}