[llvm] [SPIRV] Added constraint for SPV_INTEL_bindless_image extension (PR #160249)
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Tue Sep 23 03:24:27 PDT 2025
https://github.com/EbinJose2002 updated https://github.com/llvm/llvm-project/pull/160249
>From 85e449ca5c0ee249115c671cda7ae66270d4109a Mon Sep 17 00:00:00 2001
From: EbinJose2002 <ebin.jose at multicorewareinc.com>
Date: Fri, 11 Jul 2025 18:06:16 +0530
Subject: [PATCH 1/3] Added check for bindless_image extension
---
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 29 ++++++++++++++++++-
.../i32-in-physical64.ll | 19 ++++++++++++
2 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bindless_images/i32-in-physical64.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index ad976e5288927..a30d5b10f28d7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1738,15 +1738,42 @@ void addInstrRequirements(const MachineInstr &MI,
break;
case SPIRV::OpConvertHandleToImageINTEL:
case SPIRV::OpConvertHandleToSamplerINTEL:
- case SPIRV::OpConvertHandleToSampledImageINTEL:
+ case SPIRV::OpConvertHandleToSampledImageINTEL: {
if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_bindless_images))
report_fatal_error("OpConvertHandleTo[Image/Sampler/SampledImage]INTEL "
"instructions require the following SPIR-V extension: "
"SPV_INTEL_bindless_images",
false);
+ SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry();
+ SPIRV::AddressingModel::AddressingModel AddrModel;
+ unsigned PointerSize = ST.getPointerSize();
+ AddrModel = PointerSize == 32 ? SPIRV::AddressingModel::Physical32
+ : SPIRV::AddressingModel::Physical64;
+ SPIRVType *TyDef = GR->getSPIRVTypeForVReg(MI.getOperand(1).getReg());
+ if (!(TyDef->getOpcode() == SPIRV::OpTypeImage &&
+ MI.getOpcode() == SPIRV::OpConvertHandleToImageINTEL) &&
+ !(TyDef->getOpcode() == SPIRV::OpTypeSampler &&
+ MI.getOpcode() == SPIRV::OpConvertHandleToSamplerINTEL) &&
+ !(TyDef->getOpcode() == SPIRV::OpTypeSampledImage &&
+ MI.getOpcode() == SPIRV::OpConvertHandleToSampledImageINTEL))
+ report_fatal_error("Incorrect return type of the instruction", false);
+ SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(MI.getOperand(2).getReg());
+ if (SpvTy->getOpcode() != SPIRV::OpTypeInt) {
+ SpvTy = GR->getSPIRVTypeForVReg(SpvTy->getOperand(1).getReg());
+ }
+ unsigned Bitwidth = GR->getScalarOrVectorBitWidth(SpvTy);
+ if (!(Bitwidth == 32 && AddrModel == SPIRV::AddressingModel::Physical32) &&
+ !(Bitwidth == 64 && AddrModel == SPIRV::AddressingModel::Physical64)) {
+ report_fatal_error(
+ "Parameter value must be a 32-bit scalar in case of "
+ "Physical32 addressing model or a 64-bit scalar in case of "
+ "Physical64 addressing model",
+ false);
+ }
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_bindless_images);
Reqs.addCapability(SPIRV::Capability::BindlessImagesINTEL);
break;
+ }
case SPIRV::OpSubgroup2DBlockLoadINTEL:
case SPIRV::OpSubgroup2DBlockLoadTransposeINTEL:
case SPIRV::OpSubgroup2DBlockLoadTransformINTEL:
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bindless_images/i32-in-physical64.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bindless_images/i32-in-physical64.ll
new file mode 100644
index 0000000000000..3624f149cb491
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bindless_images/i32-in-physical64.ll
@@ -0,0 +1,19 @@
+; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_bindless_images %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+; CHECK-ERROR: LLVM ERROR: Parameter value must be a 32-bit scalar in case of Physical32 addressing model or a 64-bit scalar in case of Physical64 addressing model
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-unknown"
+
+define spir_func void @foo(i32 %in) {
+ %img = call spir_func target("spirv.Image", i32, 2, 0, 0, 0, 0, 0, 0) @_Z33__spirv_ConvertHandleToImageINTELi(i32 %in)
+ %samp = call spir_func target("spirv.Sampler") @_Z35__spirv_ConvertHandleToSamplerINTELl(i64 42)
+ %sampImage = call spir_func target("spirv.SampledImage", i64, 1, 0, 0, 0, 0, 0, 0) @_Z40__spirv_ConvertHandleToSampledImageINTELl(i64 43)
+ ret void
+}
+
+declare spir_func target("spirv.Image", i32, 2, 0, 0, 0, 0, 0, 0) @_Z33__spirv_ConvertHandleToImageINTELi(i32)
+
+declare spir_func target("spirv.Sampler") @_Z35__spirv_ConvertHandleToSamplerINTELl(i64)
+
+declare spir_func target("spirv.SampledImage", i64, 1, 0, 0, 0, 0, 0, 0) @_Z40__spirv_ConvertHandleToSampledImageINTELl(i64)
>From 4128996da3d0edfa8871309b7c939c7f07f3b838 Mon Sep 17 00:00:00 2001
From: EbinJose2002 <ebin.jose at multicorewareinc.com>
Date: Tue, 23 Sep 2025 12:55:18 +0530
Subject: [PATCH 2/3] Split checks into 3 Used MAI.Addr
---
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 33 +++++++++++--------
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index a30d5b10f28d7..692834e20e3cc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1217,8 +1217,9 @@ static void AddDotProductRequirements(const MachineInstr &MI,
}
void addInstrRequirements(const MachineInstr &MI,
- SPIRV::RequirementHandler &Reqs,
+ SPIRV::ModuleAnalysisInfo &MAI,
const SPIRVSubtarget &ST) {
+ SPIRV::RequirementHandler &Reqs = MAI.Reqs;
switch (MI.getOpcode()) {
case SPIRV::OpMemoryModel: {
int64_t Addr = MI.getOperand(0).getImm();
@@ -1745,22 +1746,28 @@ void addInstrRequirements(const MachineInstr &MI,
"SPV_INTEL_bindless_images",
false);
SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry();
- SPIRV::AddressingModel::AddressingModel AddrModel;
+ SPIRV::AddressingModel::AddressingModel AddrModel = MAI.Addr;
unsigned PointerSize = ST.getPointerSize();
AddrModel = PointerSize == 32 ? SPIRV::AddressingModel::Physical32
: SPIRV::AddressingModel::Physical64;
SPIRVType *TyDef = GR->getSPIRVTypeForVReg(MI.getOperand(1).getReg());
- if (!(TyDef->getOpcode() == SPIRV::OpTypeImage &&
- MI.getOpcode() == SPIRV::OpConvertHandleToImageINTEL) &&
- !(TyDef->getOpcode() == SPIRV::OpTypeSampler &&
- MI.getOpcode() == SPIRV::OpConvertHandleToSamplerINTEL) &&
- !(TyDef->getOpcode() == SPIRV::OpTypeSampledImage &&
- MI.getOpcode() == SPIRV::OpConvertHandleToSampledImageINTEL))
- report_fatal_error("Incorrect return type of the instruction", false);
- SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(MI.getOperand(2).getReg());
- if (SpvTy->getOpcode() != SPIRV::OpTypeInt) {
- SpvTy = GR->getSPIRVTypeForVReg(SpvTy->getOperand(1).getReg());
+ if (MI.getOpcode() == SPIRV::OpConvertHandleToImageINTEL &&
+ TyDef->getOpcode() != SPIRV::OpTypeImage) {
+ report_fatal_error("Incorrect return type for the instruction "
+ "OpConvertHandleToImageINTEL",
+ false);
+ } else if (MI.getOpcode() == SPIRV::OpConvertHandleToSamplerINTEL &&
+ TyDef->getOpcode() != SPIRV::OpTypeSampler) {
+ report_fatal_error("Incorrect return type for the instruction "
+ "OpConvertHandleToSamplerINTEL",
+ false);
+ } else if (MI.getOpcode() == SPIRV::OpConvertHandleToSampledImageINTEL &&
+ TyDef->getOpcode() != SPIRV::OpTypeSampledImage) {
+ report_fatal_error("Incorrect return type for the instruction "
+ "OpConvertHandleToSampledImageINTEL",
+ false);
}
+ SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(MI.getOperand(2).getReg());
unsigned Bitwidth = GR->getScalarOrVectorBitWidth(SpvTy);
if (!(Bitwidth == 32 && AddrModel == SPIRV::AddressingModel::Physical32) &&
!(Bitwidth == 64 && AddrModel == SPIRV::AddressingModel::Physical64)) {
@@ -1906,7 +1913,7 @@ static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI,
continue;
for (const MachineBasicBlock &MBB : *MF)
for (const MachineInstr &MI : MBB)
- addInstrRequirements(MI, MAI.Reqs, ST);
+ addInstrRequirements(MI, MAI, ST);
}
// Collect requirements for OpExecutionMode instructions.
auto Node = M.getNamedMetadata("spirv.ExecutionMode");
>From ead1d416df79f9e6b89bde5fe11fc196f1b522bf Mon Sep 17 00:00:00 2001
From: Ebin-McW <ebin.jose at multicorewareinc.com>
Date: Tue, 23 Sep 2025 15:54:17 +0530
Subject: [PATCH 3/3] Update SPIRVModuleAnalysis.cpp
---
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 692834e20e3cc..709b04cd54d36 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1747,9 +1747,6 @@ void addInstrRequirements(const MachineInstr &MI,
false);
SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry();
SPIRV::AddressingModel::AddressingModel AddrModel = MAI.Addr;
- unsigned PointerSize = ST.getPointerSize();
- AddrModel = PointerSize == 32 ? SPIRV::AddressingModel::Physical32
- : SPIRV::AddressingModel::Physical64;
SPIRVType *TyDef = GR->getSPIRVTypeForVReg(MI.getOperand(1).getReg());
if (MI.getOpcode() == SPIRV::OpConvertHandleToImageINTEL &&
TyDef->getOpcode() != SPIRV::OpTypeImage) {
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