[llvm] [DRAFT][RegisterCoalescer] Enable non-trivial rematerialization (PR #160153)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm commented:

Thanks for doing something about this huge mess. The backends were forced to lie based on the only type of remat being "trivial."

Another case I'm interested in that's nontrivial is rematerializing that requires rewriting the instruction. e.g. rematerializing only part of a value if only sub registers are demanded, or changing the use instruction to a different opcode based on register bank 

https://github.com/llvm/llvm-project/pull/160153