[llvm] [TargetLowering] Add more binops to isBinOp and isCommutativeBinOp (PR #160198)

[via llvm-commits]

https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/160198

None

>From 222f3a614d53fc449574ed9524f4c505e58847b1 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 22 Sep 2025 16:57:20 -0400
Subject: [PATCH] Add more binops to isBinOp and isCommutativeBinOp

---
 llvm/include/llvm/CodeGen/TargetLowering.h | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c2d991308d30..db225f10da38d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2997,6 +2997,8 @@ class LLVM_ABI TargetLoweringBase {
     case ISD::XOR:
     case ISD::SADDO:
     case ISD::UADDO:
+    case ISD::UADDO_CARRY:
+    case ISD::SADDO_CARRY:
     case ISD::ADDC:
     case ISD::ADDE:
     case ISD::SADDSAT:
@@ -3016,7 +3018,8 @@ class LLVM_ABI TargetLoweringBase {
     case ISD::ABDS:
     case ISD::ABDU:
       return true;
-    default: return false;
+    default:
+      return false;
     }
   }
 
@@ -3028,6 +3031,14 @@ class LLVM_ABI TargetLoweringBase {
     // These are non-commutative binops.
     switch (Opcode) {
     case ISD::SUB:
+    case ISD::SUBC:
+    case ISD::SUBE:
+    case ISD::USUBO:
+    case ISD::SSUBO:
+    case ISD::USUBO_CARRY:
+    case ISD::SSUBO_CARRY:
+    case ISD::SDIVREM:
+    case ISD::UDIVREM:
     case ISD::SHL:
     case ISD::SRL:
     case ISD::SRA:
@@ -3042,6 +3053,10 @@ class LLVM_ABI TargetLoweringBase {
     case ISD::FSUB:
     case ISD::FDIV:
     case ISD::FREM:
+    case ISD::UCMP:
+    case ISD::SCMP:
+    case ISD::SSHLSAT:
+    case ISD::USHLSAT:
       return true;
     default:
       return false;