[llvm] 6264041 - [RISCV] Use isUInt<32> instead of <= 0xffffffff. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-09-22T10:25:04-07:00
New Revision: 626404148b30944eaf2df557bfa9ea873797e0de

URL: https://github.com/llvm/llvm-project/commit/626404148b30944eaf2df557bfa9ea873797e0de
DIFF: https://github.com/llvm/llvm-project/commit/626404148b30944eaf2df557bfa9ea873797e0de.diff

LOG: [RISCV] Use isUInt<32> instead of <= 0xffffffff. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8070a512ab078..542be1c20efc0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16796,7 +16796,7 @@ static SDValue performSETCCCombine(SDNode *N,
     // addi or xori after shifting.
     uint64_t N1Int = cast<ConstantSDNode>(N1)->getZExtValue();
     uint64_t AndRHSInt = AndRHSC.getZExtValue();
-    if (OpVT == MVT::i64 && AndRHSInt <= 0xffffffff &&
+    if (OpVT == MVT::i64 && isUInt<32>(AndRHSInt) &&
         isPowerOf2_32(-uint32_t(AndRHSInt)) && (N1Int & AndRHSInt) == N1Int) {
       unsigned ShiftBits = llvm::countr_zero(AndRHSInt);
       int64_t NewC = SignExtend64<32>(N1Int) >> ShiftBits;