[llvm] [AMDGPU] Calc IsVALU correctly during UADDO/USUBO selection (PR #159814)

[via llvm-commits]

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@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdpal -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN-ISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
+; Ensure that S_UADDO_PSEUDO is selected when carryout user is S_ADD_CO_PSEUDO
+
+; GCN-ISEL-LABEL: name:   s_uaddo_pseudo
+; GCN-ISEL-LABEL: body:
+; GCN-ISEL: S_UADDO_PSEUDO
+; GCN-ISEL: S_ADD_CO_PSEUDO
+
+define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0, i32 inreg %val1) {
+; CHECK-LABEL: s_uaddo_pseudo:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_add_i32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b64 s[0:1], 1, 0
+; CHECK-NEXT:    s_cmp_lg_u64 s[0:1], 0
+; CHECK-NEXT:    s_addc_u32 s0, 1, 0
+; CHECK-NEXT:    ; return to shader part epilog
+  %pair = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val0, i32 %val1)
+  %carryout = extractvalue {i32, i1} %pair, 1
+  %add_overflow = sext i1 %carryout to i32
+  %cmp_carryout = icmp ult i32 0, %add_overflow
+  %zext_carryout = zext i1 %cmp_carryout to i32
+  %result = add i32 %zext_carryout, 1
+  ret i32 %result
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LU-JOHN wrote:

I've simplified the IR with llvm-reduce.  This PR fixes/improves code generation for scalar 32-bit add/subs.

This PR is in preparation for #152992, which will be dealt with in https://github.com/llvm/llvm-project/pull/155255. #155255 will split a 64-bit add into UADDO/UADDO_CARRY, so that the carryout from the 64-bit add can be utilized.

https://github.com/llvm/llvm-project/pull/159814