[llvm] [X86][MC][AsmParser] Reject H-byte regs with VEX/EVEX-encoded 8-bit RR (NDD) (PR #160039)

[via llvm-commits]

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@@ -4044,6 +4044,24 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
     }
   }
 
+  unsigned Enc = TSFlags & X86II::EncodingMask;
+  if (Enc == X86II::VEX || Enc == X86II::EVEX || Enc == X86II::XOP) {
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woruyu wrote:

Thanks for the question. I don’t have a realistic VEX/XOP reproducer here. The concrete failure I'm fixing is EVEX (e.g. NDD/NF 8-bit RR/MR forms) selecting for cases like `add ah, ah, ah`.I’ve narrowed the parser diagnostic to EVEX.If/when REX2 becomes exposed via TSFlags, we can add it similarly.

https://github.com/llvm/llvm-project/pull/160039