[llvm] [RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced (PR #159715)

[Luke Lau via llvm-commits]

================
@@ -184,11 +181,10 @@ entry:
 define i32 @vdotqsu_vx_constant(<vscale x 16 x i8> %a) {
 ; CHECK-LABEL: vdotqsu_vx_constant:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT:    vsext.vf2 v16, v8
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vsext.vf4 v16, v8
 ; CHECK-NEXT:    li a0, 123
-; CHECK-NEXT:    vwmul.vx v8, v16, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vmul.vx v8, v16, a0
----------------
lukel97 wrote:

> Overall, there is a slight reduction in the number of instructions.

>From our measurements vsetvli instructions usually aren't the bottleneck. I think in this example the increased number of uops issued from the higher LMUL vsext will likely outweigh benefit or removing the vsetvli toggle.

https://github.com/llvm/llvm-project/pull/159715