[llvm] [RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in RISCVMatInt. NFC (PR #159864)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Sun Sep 21 20:24:36 PDT 2025

Previous message: [llvm] [RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in RISCVMatInt. NFC (PR #159864)
Next message: [llvm] [RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in RISCVMatInt. NFC (PR #159864)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/159864

Previous message: [llvm] [RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in RISCVMatInt. NFC (PR #159864)
Next message: [llvm] [RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in RISCVMatInt. NFC (PR #159864)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list