[llvm] f65d5a7 - [DAG] Skip `mstore` combine for `<1 x ty>` vectors (#159915)

[via llvm-commits]

Author: Abhishek Kaushik
Date: 2025-09-21T11:06:49-07:00
New Revision: f65d5a7a56c31aaa982d3d4717481d739f2f9ecb

URL: https://github.com/llvm/llvm-project/commit/f65d5a7a56c31aaa982d3d4717481d739f2f9ecb
DIFF: https://github.com/llvm/llvm-project/commit/f65d5a7a56c31aaa982d3d4717481d739f2f9ecb.diff

LOG: [DAG] Skip `mstore` combine for `<1 x ty>` vectors (#159915)

Fixes #159912

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AArch64/combine-storetomstore.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0c773e7dcb5de..91ae7b0b28ba7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22690,6 +22690,12 @@ static SDValue foldToMaskedStore(StoreSDNode *Store, SelectionDAG &DAG,
   SDValue StorePtr = Store->getBasePtr();
   SDValue StoreOffset = Store->getOffset();
   EVT VT = Store->getMemoryVT();
+
+  // Skip this combine for non-vector types and for <1 x ty> vectors, as they
+  // will be scalarized later.
+  if (!VT.isVector() || VT.isScalableVector() || VT.getVectorNumElements() == 1)
+    return SDValue();
+
   unsigned AddrSpace = Store->getAddressSpace();
   Align Alignment = Store->getAlign();
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();

diff  --git a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
index 6ab2d7c2d7857..aaa6ba36561df 100644
--- a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
@@ -1135,3 +1135,19 @@ define void @test_masked_store_unaligned_v8i64(<8 x i64> %data, ptr %ptr, <8 x i
   store <8 x i64> %sel, ptr %ptr_vec, align 1
   ret void
 }
+
+define void @PR159912(<1 x i1> %arg, ptr %ptr) #0 {
+; SVE-LABEL: PR159912:
+; SVE:       // %bb.0:
+; SVE-NEXT:    tst w0, #0x1
+; SVE-NEXT:    ldr d0, [x1]
+; SVE-NEXT:    csetm x8, ne
+; SVE-NEXT:    fmov d1, x8
+; SVE-NEXT:    bic v0.8b, v0.8b, v1.8b
+; SVE-NEXT:    str d0, [x1]
+; SVE-NEXT:    ret
+  %load = load <1 x i64>, ptr %ptr, align 8
+  %select = select <1 x i1> %arg, <1 x i64> zeroinitializer, <1 x i64> %load
+  store <1 x i64> %select, ptr %ptr, align 8
+  ret void
+}