[llvm] [DAG] Add ISD::VECTOR_COMPRESS handling in computeKnownBits/ComputeNumSignBits (PR #159692)

[Simon Pilgrim via llvm-commits]

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@@ -3480,6 +3480,20 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
         break;
     }
     break;
+  case ISD::VECTOR_COMPRESS: {
+    SDValue Vec = Op.getOperand(0);
+    SDValue PassThru = Op.getOperand(2);
+
+    Known.Zero.setAllBits();
+    Known.One.setAllBits();
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RKSimon wrote:

The setAllBits calls can now be removed

https://github.com/llvm/llvm-project/pull/159692