[clang] [llvm] [ARM] enable FENV_ACCESS pragma support for hard-float targets (PR #137101)

[David Green via llvm-commits]

davemgreen wrote:

Am I right that the bits of FPSCR that are read by the instruction are just the rounding mode? Can we add a new register for just those bits, like FPSCR_NZCV. FPSCR_RM would alias with FPSCR but not FPSCR_NZCV.
```
def FPSCR_RM   : ARMReg<3,  "fpscr_rm"> {
  let Aliases = [FPSCR];
}
```
I didn't try it past a few of the basic tests in llvm. The important part is that we don't hoist the instructions that use the rounding mode past an instructions that sets it. (And an instruction that sets FPSCR doesn't get moved past one that sets FPSCR_NZCV).

The alternative might be to try and make fpscr_rm and fpscr_nzcv SubRegs of fpscr, which might work but ran into other issues when I tried it.

> As for how to organize the patches after separation: should each individual patch have a separate PR?

Ideally yeah, So long as they are individually testable. It is more difficult to review larger changes and get them to stick in llvm without causing issues and needing to be reverted.

https://github.com/llvm/llvm-project/pull/137101