[llvm] [DAG] Skip `mstore` combine for `<1 x ty>` vectors (PR #159915)
Abhishek Kaushik via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 20 03:46:58 PDT 2025
https://github.com/abhishek-kaushik22 updated https://github.com/llvm/llvm-project/pull/159915
>From e5f0e4da9cf83bb4782af829767eb5ef619f324c Mon Sep 17 00:00:00 2001
From: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: Sat, 20 Sep 2025 15:42:03 +0530
Subject: [PATCH 1/3] [DAG] Skip `mstore` combine for `<1 x ty>` vectors
Fixes #159912
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 ++++++
.../CodeGen/AArch64/combine-storetomstore.ll | 20 +++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 97a3d36a67103..1f76b0ea5008d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22603,6 +22603,12 @@ static SDValue foldToMaskedStore(StoreSDNode *Store, SelectionDAG &DAG,
SDValue StorePtr = Store->getBasePtr();
SDValue StoreOffset = Store->getOffset();
EVT VT = Store->getMemoryVT();
+
+ // Skip this combine for non-vector types and for <1 x ty> vectors, as they
+ // will be scalarized later.
+ if (!VT.isVector() || VT.getVectorNumElements() == 1)
+ return SDValue();
+
unsigned AddrSpace = Store->getAddressSpace();
Align Alignment = Store->getAlign();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
diff --git a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
index c2e54d3d39394..f63e648f034eb 100644
--- a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
@@ -1191,3 +1191,23 @@ define void @test_masked_store_unaligned_v8i64(<8 x i64> %data, ptr %ptr, <8 x i
store <8 x i64> %sel, ptr %ptr_vec, align 1
ret void
}
+
+ at global = external global i64
+
+define void @PR159912(<1 x i1> %arg) #0 {
+; SVE-LABEL: PR159912:
+; SVE: // %bb.0:
+; SVE-NEXT: adrp x8, :got:global
+; SVE-NEXT: tst w0, #0x1
+; SVE-NEXT: ldr x8, [x8, :got_lo12:global]
+; SVE-NEXT: csetm x9, ne
+; SVE-NEXT: fmov d1, x9
+; SVE-NEXT: ldr d0, [x8]
+; SVE-NEXT: bic v0.8b, v0.8b, v1.8b
+; SVE-NEXT: str d0, [x8]
+; SVE-NEXT: ret
+ %load = load <1 x i64>, ptr @global, align 8
+ %select = select <1 x i1> %arg, <1 x i64> zeroinitializer, <1 x i64> %load
+ store <1 x i64> %select, ptr @global, align 8
+ ret void
+}
>From 2e1f7087c8427de65d83d8bdced1bf105d2d9be7 Mon Sep 17 00:00:00 2001
From: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: Sat, 20 Sep 2025 15:45:49 +0530
Subject: [PATCH 2/3] Update combine-storetomstore.ll
---
.../CodeGen/AArch64/combine-storetomstore.ll | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
index f63e648f034eb..d54140d4749a5 100644
--- a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
@@ -1192,22 +1192,18 @@ define void @test_masked_store_unaligned_v8i64(<8 x i64> %data, ptr %ptr, <8 x i
ret void
}
- at global = external global i64
-
-define void @PR159912(<1 x i1> %arg) #0 {
+define void @PR159912(<1 x i1> %arg, ptr %ptr) #0 {
; SVE-LABEL: PR159912:
; SVE: // %bb.0:
-; SVE-NEXT: adrp x8, :got:global
; SVE-NEXT: tst w0, #0x1
-; SVE-NEXT: ldr x8, [x8, :got_lo12:global]
-; SVE-NEXT: csetm x9, ne
-; SVE-NEXT: fmov d1, x9
-; SVE-NEXT: ldr d0, [x8]
+; SVE-NEXT: ldr d0, [x1]
+; SVE-NEXT: csetm x8, ne
+; SVE-NEXT: fmov d1, x8
; SVE-NEXT: bic v0.8b, v0.8b, v1.8b
-; SVE-NEXT: str d0, [x8]
+; SVE-NEXT: str d0, [x1]
; SVE-NEXT: ret
- %load = load <1 x i64>, ptr @global, align 8
+ %load = load <1 x i64>, ptr %ptr, align 8
%select = select <1 x i1> %arg, <1 x i64> zeroinitializer, <1 x i64> %load
- store <1 x i64> %select, ptr @global, align 8
+ store <1 x i64> %select, ptr %ptr, align 8
ret void
}
>From 70ed31a8c80da3a5d18ecacfe53bea4fe7940eea Mon Sep 17 00:00:00 2001
From: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: Sat, 20 Sep 2025 16:16:43 +0530
Subject: [PATCH 3/3] Update DAGCombiner.cpp
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1f76b0ea5008d..1aabb6e845e35 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22606,7 +22606,7 @@ static SDValue foldToMaskedStore(StoreSDNode *Store, SelectionDAG &DAG,
// Skip this combine for non-vector types and for <1 x ty> vectors, as they
// will be scalarized later.
- if (!VT.isVector() || VT.getVectorNumElements() == 1)
+ if (!VT.isVector() || VT.isScalableVector() || VT.getVectorNumElements() == 1)
return SDValue();
unsigned AddrSpace = Store->getAddressSpace();
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