[llvm] [AMDGPU] Allow folding of non-subregs through REG_SEQUENCE (PR #151033)

[Matt Arsenault via llvm-commits]

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@@ -1465,6 +1477,33 @@ void SIFoldOperandsImpl::foldOperand(
       return;
   }
 
+  if (!FoldingImmLike && OpToFold.isReg() && ST->needsAlignedVGPRs()) {
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arsenm wrote:

This is too much special casing for an unrelated hack (really we should have an aligned 32-bit register class for this case)

If you use getRegClassConstraintEffectForVReg instead of checking the specific operand to compute the constraint, do you avoid the need for this.

https://github.com/llvm/llvm-project/pull/151033